CYD18S72V-100BBI Cypress Semiconductor Corp, CYD18S72V-100BBI Datasheet - Page 4

• Manufacturer Part Number: CYD18S72V-100BBI
• Description: IC,SYNC SRAM,256KX72,CMOS,BGA,484PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S72V-100BBI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 18M (256K x 72)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number : 38-06069 Rev. *K
PORTSTD[1:0]
DQ
LowSPD
CNT/MSK
READY
CNTRST
CNTINT
FTSEL
BE
CNTEN
BUSY
VREF
WRP
Left Port
A
REV
RET
VDDIO
ADS
CE0
CE1
0L
0L
0L
R/W
INT
OE
C
–A
–DQ
–BE
L
[2,4]
L
L
L
L
L
L
L
[2,3]
L
L
L
[2,3]
17L
[9]
[8]
L
L
[2,5]
[9]
[2,4]
L
L
L
[2,3]
[2,5]
[2,4]
L
[10]
L
71L
[9]
7L
L
L
[8]
[8]
L
[2,4]
TRST
MRST
PORTSTD[1:0]
[2,5]
DQ
LowSPD
CNT/MSK
READY
CNTRST
CNTINT
BE
FTSEL
CNTEN
Right Port
BUSY
VREF
WRP
A
REV
RET
VDDIO
ADS
CE0
CE1
0R
0R
0R
R/W
INT
OE
C
–A
–DQ
–BE
R
[2,4]
R
R
R
R
R
R
R
R
R
R
[2,3]
R
R
[2,3]
17R
[9]
[8]
[2,4]
[2,5]
R
[9]
R
R
[2,3]
[2,5]
R
R
[2,4]
[10]
71R
R
[9]
R
7R
[8]
[8]
R
[2,4]
Address Inputs.
Byte Enable Inputs. Asserting these signals enables Read and Write operations
to the corresponding bytes of the memory array.
Port Busy Output. When the collision is detected, a BUSY is asserted.
Input Clock Signal.
Active Low Chip Enable Input.
Active High Chip Enable Input.
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between
ports. The upper two memory locations can be used for message passing. INT
asserted LOW when the right port writes to the mailbox location of the left port, and
vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of
its mailbox.
Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
Port Address/Control/Data I/O Standard Select Input.
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from
the dual-port memory array.
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
Port Counter Wrap Input. After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
Port Counter Retransmit Input. Counter control input.
Flow-Through Select. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
Port External High-Speed IO Reference Input.
Port IO Power Supply.
Reserved pins for future features.
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
JTAG Reset Input.
Description
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