CYD18S72V-100BBI Cypress Semiconductor Corp, CYD18S72V-100BBI Datasheet - Page 15

• Manufacturer Part Number: CYD18S72V-100BBI
• Description: IC,SYNC SRAM,256KX72,CMOS,BGA,484PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S72V-100BBI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 18M (256K x 72)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Waveforms
Read Cycle
Notes
Document Number : 38-06069 Rev. *K
Master Reset
29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31. The output is disabled (high-impedance state) by CE = V
32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
Numbers are for reference only.
ADDRESS
DATA
BE0–BE7
R/W
CLK
OUT
OE
CE
[12, 29, 30, 31, 32]
t
RSF
t
t
t
t
SW
SA
SB
SC
A
t
RS
n
t
t
t
t
INACTIVE
RSS
t
HB
HW
HA
t
HC
(continued)
CH2
1 Latency
t
RSR
t
CYC2
t
CKLZ
t
CL2
IH
A
following the next rising edge of the clock.
n+1
ACTIVE
t
CD2
IL
with CNT/MSK = V
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
t
OE
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Page 15 of 26
Q
n+2
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