CY7C68013A-56PVXCT Cypress Semiconductor Corp, CY7C68013A-56PVXCT Datasheet - Page 50
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CY7C68013A-56PVXCT
Manufacturer Part Number
CY7C68013A-56PVXCT
Description
CY7C68013A-56PVXCT
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Datasheet
1.CY7C68013A-56PVXC.pdf
(62 pages)
Specifications of CY7C68013A-56PVXCT
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Details
Other names
CY7C68013A56PVXCT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56PVXCT
Manufacturer:
CYPRESS
Quantity:
9 103
10.17 Sequence Diagram
10.17.1 Single and Burst Synchronous Read Example
Figure 29
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
■
■
■
Document #: 38-08032 Rev. *M
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications). Note
that t
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO. Note: the data is pre-fetched and is driven on the bus
when SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
t
the IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the deassertion of the SLRD signal).
SRD
FIFO POINTER
FLAGS
FIFO DATA BUS
FIFOADR
SLRD
SLCS
DATA
IFCLK
SLOE
SFA
(time from asserting the SLRD signal to the rising edge of
shows the timing relationship of the SLAVE FIFO
has a minimum of 25 ns. This means when IFCLK is
Not Driven
t=0
IFCLK
N
Figure 29. Slave FIFO Synchronous Read Sequence and Timing Diagram
t=1
SLOE
t
SFA
t
OEon
Figure 30. Slave FIFO Synchronous Sequence of Events Diagram
Data Driven: N
t=2
Driven: N
t
SRD
IFCLK
N
t
IFCLK
t
XFD
t=3
t
SLRD
RDH
t
XFLG
t
OEoff
N+1
t=4
N+1
t
IFCLK
N+1
FAH
RDH
SLOE
SLRD
(time
Not Driven
IFCLK
t
N+1
T=0
SFA
■
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
t
OEon
SLOE
If the SLCS signal is used, it must be asserted before SLRD is
asserted (The SLCS and SLRD signals must both be asserted
to start a valid read condition).
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
T=2
>= t
T=1
N+1
IFCLK
N+1
SRD
N+1
SLRD
t
XFD
N+2
N+2
IFCLK
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
N+2
N+3
N+3
IFCLK
XFD
t
XFD
(measured from the rising edge of
N+4
N+4
IFCLK
N+3
SLRD
[20]
t
>= t
XFD
RDH
N+4
N+4
IFCLK
t
N+4
OEoff
SLOE
Page 50 of 62
T=3
T=4
t
FAH
Not Driven
IFCLK
N+4
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