CY7C67300-100AXAT Cypress Semiconductor Corp, CY7C67300-100AXAT Datasheet - Page 53

• Manufacturer Part Number: CY7C67300-100AXAT
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXAT

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 84. Mode Select Definition
Reserved
Write all reserved bits with ’0’.
IDE Start Address Register [0xC04A] [R/W]
Table 85. IDE Start Address Register
Register Description
The IDE Start Address register holds the start address for an IDE
block transfer. This register is byte addressed and IDE block
transfers are 16-bit words, therefore the LSB of the start address
is ignored. Block transfers begin at IDE Start Address and end
with the final word at IDE Stop Address. When IDE Start Address
equals IDE Stop Address, the block transfer moves one word of
data.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Mode Select [2:0]
000
001
010
100
101
011
110
111
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
R/W
R/W
13
0
5
0
Disable IDE port operations
IDE PIO Mode 0
IDE PIO Mode 1
IDE PIO Mode 2
IDE PIO Mode 3
IDE PIO Mode 4
R/W
R/W
12
0
4
0
Reserved
Reserved
Mode
Address...
...Address
The hardware keeps an internal memory address counter. The
two MSBs of the addresses are not modified by the address
counter. Therefore, the IDE Start Address and IDE Stop Address
must reside within the same 16K byte block.
Address (Bits [15:0])
The Address field sets the start address for an IDE block transfer.
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
CY7C67300
Page 53 of 99
R/W
R/W
8
0
0
0
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