CY7C67300-100AXAT Cypress Semiconductor Corp, CY7C67300-100AXAT Datasheet - Page 22

• Manufacturer Part Number: CY7C67300-100AXAT
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXAT

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB Diagnostic Register [0xC03C] [R/W]
Table 31. USB Diagnostic Register
Register Description
The USB Diagnostic register provides control of diagnostic
modes. It is intended for use by device characterization tests, not
for normal operations. This register is read/write by the on-chip
CPU but is write-only via the HPI port.
Port 2B Diagnostic Enable (Bit 15)
The Port 2B Diagnostic Enable bit enables or disables Port 2B
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK,
SE0, RSF, RSL, PRD
0: Do not apply test conditions
Port 2A Diagnostic Enable (Bit 14)
The Port 2A Diagnostic Enable bit enables or disables Port 2A
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK,
SE0, RSF, RSL, PRD
0: Do not apply test conditions
Port 1B Diagnostic Enable (Bit 13)
The Port 1B Diagnostic Enable bit enables or disables Port 1B
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK,
SE0, RSF, RSL, PRD
0: Do not apply test conditions
Port 1A Diagnostic Enable (Bit 12)
The Port 1A Diagnostic Enable bit enables or disables Port 1A
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK,
SE0, RSF, RSL, PRD
0: Do not apply test conditions
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
...Reserved
Diagnostic
Port 2B
Enable
R/W
15
0
7
0
-
Diagnostic
Pull-down
Port 2A
Enable
Enable
R/W
R/W
14
0
6
0
Diagnostic
LS Pull-up
Port 1B
Enable
Enable
R/W
R/W
13
0
5
0
Diagnostic
FS Pull-up
Port 1A
Enable
Enable
R/W
R/W
12
0
4
0
Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed pull
down resistors (pull down on both D+ and D–) for testing.
1: Enable pull down resistors on both D+ and D–
0: Disable pull down resistors on both D+ and D–
LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull
up resistor (pull up on D–) for testing.
1: Enable low-speed pull up resistor on D–
0: Pull-up resistor is not connected on D–
FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull
up resistor (pull up on D+) for testing.
1: Enable full-speed pull up resistor on D+
0: Pull up resistor is not connected on D+
Force Select (Bits [2:0])
The Force Select field bit selects several different test condition
states on the data lines (D+/D–). Refer to
Table 32. Force Select Definition
Reserved
Write all reserved bits with ’0’.
Force Select [2:0]
Reserved
11
0
3
0
-
-
1xx
01x
001
000
R/W
10
0
2
0
-
Reserved...
Force Select
R/W
Data Line State
9
0
1
0
-
Assert SE0
Toggle JK
Assert K
Assert J
Table 32
CY7C67300
Page 22 of 99
R/W
for details.
8
0
0
0
-
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