CY7C4285V-15ASXI Cypress Semiconductor Corp, CY7C4285V-15ASXI Datasheet - Page 15
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CY7C4285V-15ASXI
Manufacturer Part Number
CY7C4285V-15ASXI
Description
CY7C4285V-15ASXI
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C4285V-15ASXI
Function
Synchronous
Memory Size
1.1K (64 x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
10ns
Word Size
18b
Organization
64Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
35mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4285V-15ASXI
Manufacturer:
CIRRUS
Quantity:
872
Company:
Part Number:
CY7C4285V-15ASXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document Number: 38-06012 Rev. *D
Notes
23. When t
24. t
t
the rising edge of RCLK and the rising edge of WCLK is less than t
CLK
SKEW1
Q
D
Q
D
0
0
WCLK
0
0
WCLK
RCLK
RCLK
–Q
–D
+ t
WEN
WEN
REN
–D
–Q
REN
OE
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
SKEW2
OE
SKEW2
EF
17
FF
17
17
17
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
> minimum specification, t
t
DS
DATA IN OUTPUT REGISTER
t
LOW
SKEW1
t
ENS
[24]
t
ENS
NO WRITE
D0
t
SKEW2
(continued)
t
ENH
t
FRL
FRL
[23]
t
(maximum) = t
WFF
t
t
A
ENH
Figure 10. Empty Flag Timing
CLK
t
Figure 11. Full Flag Timing
REF
+ t
SKEW2
t
SKEW1
DS
. When t
, then FF may not change state until the next WCLK rising edge.
DATA WRITE
SKEW2
t
A
t
REF
< minimum specification, t
DATA READ
t
DS
t
t
SKEW1
WFF
t
ENS
[24]
t
ENS
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
D1
t
SKEW2
t
NO WRITE
ENH
FRL
t
(maximum) = either 2 × t
FRL
[23]
t
WFF
t
t
A
ENH
D0
NEXT DATA READ
t
REF
DATA WRITE
CLK
Page 15 of 24
+ t
SKEW2
or
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