CY7C4221-15AXC Cypress Semiconductor Corp, CY7C4221-15AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C4221-15AXC
• Description: IC,FIFO,1KX9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4221-15AXC

• Function: Synchronous
• Memory Size: 9K (1K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 8Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 1Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-06016 Rev. *F
Notes
(if applicable)
22. t
23. t
24. PAE offset = n.
25. If a read is performed on this rising edge of the read clock, there are Empty + (n – 1) words in the FIFO when PAE goes LOW.
(if applicable)
the rising edge of RCLK and the rising edge of WCLK is less than t
and the rising RCLK is less than t
WEN2
SKEW1
SKEW2
WEN2
Q
D
WCLK
WEN1
REN1,
WCLK
RCLK
WEN1
REN1,
REN2
RCLK
0
0
REN2
PAE
–Q
–D
OE
FF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
8
8
Data in Output Register
t
t
LOW
SKEW1
CLKH
[22]
t
ENS
NO Write
SKEW2
t
SKEW2
, then PAE may not change state until the next RCLK.
Figure 11. Programmable Almost Empty Flag Timing
t
WFF
t
t
A
ENH
t
t
ENS
ENS
[23]
t
t
ENH
ENH
t
CLKL
NO Write
Figure 10. Full Flag Timing
t
DS
SKEW1
t
PAE
Note
24
, then FF may not change state until the next WCLK rising edge.
Data Write
Data Read
t
ENS
t
t
WFF
SKEW1
CY7C4421 / 4201 / 4211 / 4221
[22]
N + 1 Words
t
ENS
INFIFO
t
ENS
NO Write
CY7C4231 / 4241 / 4251
t
ENH
t
WFF
t
t
A
ENH
Note
25
Next Data Read
Data Write
t
PAE
Page 14 of 23
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