CY7C1470BV33-200BZC Cypress Semiconductor Corp, CY7C1470BV33-200BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1470BV33-200BZC
• Description: CY7C1470BV33-200BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470BV33-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
CY7C1472BV33,
CY7C1474BV33) (or a subset for byte write operations, see
“Partial Write Cycle Description” on page 11
latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
BW
CY7C1470BV33,
provides Byte Write capability that is described in
Cycle Description” on page
(WE) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Because
CY7C1474BV33 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQ and DQP
(DQ
CY7C1472BV33,
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQ
CY7C1470BV33, DQ
DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in
on page
ZZ Mode Electrical Characteristics
Document #: 001-15031 Rev. *C
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d
a,b,c,d
a,b,c,d
Parameter
8. When ADV/LD is driven HIGH on the subsequent
/DQP
/DQP
for CY7C1470BV33, BW
the
/DQP
a,b,c,d
a,b,c,d
CY7C1470BV33,
for
a,b,c,d,e,f,g,h
CY7C1472BV33,
and
and
for CY7C1470BV33, DQ
for CY7C1470BV33, DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b
/DQP
CY7C1474BV33)
DQ
DQ
11. Asserting the Write Enable input
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b
for
Description
a,b
for CY7C1472BV33, and
for CY7C1472BV33, and
CY7C1472BV33,
“Single Write Accesses”
CY7C1474BV33)
and
/DQP
/DQP
a,b,c,d
for details) inputs is
a,b,c,d,e,f,g,h
CY7C1474BV33
a,b,c,d,e,f,g,h
signals.
a,b
a,b
/DQP
“Partial Write
/DQP
/DQP
a,b,c,d
a,b
a,b
The
and
are
for
for
for
for
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
clock rise, the Chip Enables (CE
are ignored and the burst counter is incremented. The correct
BW (BW
and BW
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Table 2. Interleaved Burst Address Table
(MODE = Floating or V
Table 3. Linear Burst Address Table (MODE = GND)
DD
DD
− 0.2V
− 0.2V
Address
Test Conditions
Address
A1,A0
A1,A0
First
First
00
01
10
11
3
00
01
10
11
a,b,c,d,e,f,g,h
, must remain inactive for the duration of t
CY7C1472BV33, CY7C1474BV33
a,b,c,d
for CY7C1470BV33, BW
for CY7C1474BV33) inputs must be driven
Address
Address
Second
Second
A1,A0
A1,A0
01
00
10
11
DD
01
10
11
00
)
1
, CE
2t
Min
Address
Address
CYC
CY7C1470BV33
0
A1,A0
2
Third
A1,A0
Third
, and CE
10
11
00
01
10
11
00
01
a,b
for CY7C1472V33,
2t
2t
Max
120
3
CYC
CYC
) and WE inputs
ZZREC
Address
Address
Fourth
Page 9 of 30
Fourth
A1,A0
A1,A0
10
01
00
11
00
01
10
11
after the
Unit
1
mA
ns
ns
ns
ns
, CE
2
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