CY7C1460AV25-200BZXI Cypress Semiconductor Corp, CY7C1460AV25-200BZXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1460AV25-200BZXI
• Description: CY7C1460AV25-200BZXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1460AV25-200BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 36M (1M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
are common I/O devices, data should not be driven into the
device while the outputs are active. The output enable (OE) can
be deasserted HIGH before presenting data to the DQ and DQP
(DQ
DQ
CY7C1462AV25) inputs. Doing so will three-state the output
drivers.
(DQ
DQ
CY7C1462AV25) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the
Accesses
subsequent clock rise, the chip enables (CE
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
for CY7C1460AV25 and BW
be driven in each cycle of the burst write in order to write the
correct bytes of data.
ZZ Mode Electrical Characteristics
Document Number: 38-05354 Rev. *G
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b,c,d
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
Parameter
/DQP
/DQP
section above. When ADV/LD is driven HIGH on the
As
a,b,c,d
a,b,c,d
/DQP
/DQP
a
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d,e,f,g,h
safety
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b
precaution,
for CY7C1462AV25) inputs must
for CY7C1464AV25, BW
Description
for
for
DQ
1
CY7C1464AV25,
CY7C1464AV25,
, CE
a,b
a,b
Single Write
2
and
/DQP
/DQP
, and CE
a,b
a,b
a,b,c,d
DQP
ZZ  V
ZZV
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
for
for
3
)
DD
DD
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
 0.2 V
 0.2 V
Test Conditions
Address
Address
A1, A0
A1, A0
First
First
00
01
10
11
00
01
10
11
3
, must remain inactive for the duration of t
Address
Second
A1, A0
Address
Second
A1, A0
01
10
11
00
01
00
11
10
2t
DD
Min
CYC
–
–
–
0
Address
A1, A0
Third
)
Address
A1, A0
10
00
01
11
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Third
10
00
01
11
2t
2t
Max
100
CYC
CYC
–
–
ZZREC
Address
Address
Fourth
A1, A0
Fourth
Page 9 of 29
A1, A0
00
01
10
Unit
11
mA
11
10
01
00
ns
ns
ns
ns
after the
1
, CE
2
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