CY7C1460AV25-250AXCT Cypress Semiconductor Corp, CY7C1460AV25-250AXCT Datasheet
CY7C1460AV25-250AXCT
Specifications of CY7C1460AV25-250AXCT
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CY7C1460AV25-250AXCT Summary of contents
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... CY7C1464AV25 available in lead-free and non-lead-free 209-ball FBGA package • IEEE 1149.1 JTAG-Compatible Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram–CY7C1460AV25 (1M x 36) ADDRESS A0, A1, A REGISTER 0 MODE CLK ...
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... REGISTER A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control 250 MHz 200 MHz 2.6 3.2 435 385 120 120 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DQs DQP T ...
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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 54 DDQ DQa DQa DQPa CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DDQ DQP 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa 59 DQa DDQ ...
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... DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M MODE A Document #: 38-05354 Rev. *D CY7C1460AV25 (1M × 36 CEN CLK TDI A1 TDO TCK TMS CY7C1462AV25 (2M × 18 CEN ...
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... DD DD DDQ MODE A NC/72M TDI Pin Description controls DQ a and DQP , BW controls DQ and DQP and DQP BW controls DQ and DQP CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DQb DQb 3 BWS DQb BWS DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf ...
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... The direction of the pins is X –DQ are placed in a tri-state condition. The outputs are automati controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 . During [31:0] , DQP is controlled DQP is controlled Page [+] Feedback ...
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... HIGH on the subsequent clock rise, the chip enables ( and counter is incremented. The correct BW (BW CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 , CE 1 for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b a,b for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b a,b for CY7C1464AV25, BW for a,b,c,d for CY7C1462AV25) signals ...
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... CY7C1460AV25, BW for CY7C1460AV25 and BW a,b,c,d CY7C1462AV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” ...
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... Partial Write Cycle Description Function (CY7C1460AV25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ and DQP ) c c Write Bytes c, a Write Bytes c, b Write Bytes Write Byte d – (DQ ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...
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... Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. Document #: 38-05354 Rev. *D CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller Shift-DR state ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 TDOV Min. Max. Unit MHz ...
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... I DDQ CY7C1462AV25 CY7C1464AV25 (1M ×36) (2M ×18) (512K ×72) 000 000 000 01011 01011 01011 001000 001000 001000 100111 010111 110111 00000110100 00000110100 1 1 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 – 0.2 DDQ 0.9V 50Ω 50Ω 20pF O Min. Max. Unit 1.7 V 2.1 V 1.6 V 0.4 V 0 ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05354 Rev. *D Bit Size (x36) Bit Size (x18 – – Description CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit Size (x72 – 138 Page [+] Feedback ...
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... FBGA Boundary Scan Order CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18) Bit# Ball ID Bit N10 28 4 P11 P10 34 10 R10 35 11 R11 36 12 H11 37 13 N11 38 14 M11 39 15 L11 40 16 K11 41 17 J11 42 18 M10 43 19 L10 44 20 K10 45 21 J10 46 22 ...
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... C2 A11 91 C1 A10 100 H2 C7 101 H1 B7 102 J2 A7 103 J1 D6 104 K1 G6 105 N6 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit# Ball ID 106 K3 107 K4 108 K6 109 K2 110 L2 111 L1 112 M2 113 M1 114 N2 115 N1 116 P2 117 P1 118 R2 119 R1 120 T2 121 T1 122 U2 123 U1 124 V2 125 V1 126 W2 ...
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... All speed grades DD ≥ V ≤ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Ambient Temperature DDQ 0°C to +70°C 2.5V –5%/+5% 1. Min. Max. 2.375 2.625 2.375 V DD 1.7 1.9 2.0 1 ...
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... V OUTPUT DDQ GND 351Ω INCLUDING JIG AND SCOPE ( 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND SCOPE (b) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 165 FBGA 209 FBGA Max. Max. Unit 165 FBGA 209 FBGA Package Package Unit 20.8 25.31 ° ...
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... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ = 1.8V. DDQ CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 –200 –167 Max. Min. Max. Unit ...
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... Q(A3) Q(A4) READ D(A5) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE is LOW. When CE is HIGH,CE is HIGH CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 OEV CHZ Q(A4+1) D(A5) Q(A6) t DOH t OELZ READ WRITE DESELECT Q(A6) D(A7 ...
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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05354 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Page [+] Feedback ...
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... CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1462AV25-167AXC CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1462AV25-167BZC CY7C1460AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1462AV25-167BZXC CY7C1464AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1464AV25-167BGXC CY7C1460AV25-167AXI 51-85050 100-Pin Thin Quad Flat Pack ( ...
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... CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1462AV25-250AXC CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1462AV25-250BZC CY7C1460AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1462AV25-250BZXC CY7C1464AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1464AV25-250BGXC CY7C1460AV25-250AXI 51-85050 100-Pin Thin Quad Flat Pack ( ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 1.40±0.05 12°±1° SEE DETAIL (8X) 0 ...
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... Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 38-05354 Rev. *D 165-ball FBGA ( 1.4 mm) (51-85165 0.15(4X) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 51-85165-*A Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 209-ball FBGA ( 1.76 mm) (51-85167) CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 ...
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... Document History Page Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 REV. ECN No. Issue Date ** 254911 See ECN *A 303533 See ECN *B 331778 See ECN *C 417547 See ECN *D 473650 See ECN Document #: 38-05354 Rev. *D Orig ...