CY7C144-55JXCT Cypress Semiconductor Corp, CY7C144-55JXCT Datasheet - Page 4

• Manufacturer Part Number: CY7C144-55JXCT
• Description: CY7C144-55JXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C144-55JXCT

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (8K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Selection Guide
Table 2. Pin Definitions
Document #: 38-06034 Rev. *H
Maximum Access Time
Maximum Operating Current
Maximum Standby Current for I
I/O
A
CE
OE
R/W
SEM
INT
BUSY
M/S
V
GND
Left Port
0L12L
CC
0L7L(8L)
L
L
L
L
L
L
I/O
A
CE
OE
R/W
SEM
INT
BUSY
Right Port
0R12R
0R7R(8R)
R
R
R
Description
R
R
R
Data bus input/output
Address lines
Chip enable
Output enable
Read/Write enable
Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant
bits of the address lines will determine which semaphore to write or read. The I/O
to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INT
1FFE. INT
Busy flag
Master or Slave select
Power
Ground
SB1
R
is set when left port writes location 1FFF and is cleared when right port reads location 1FFF.
L
is set when right port writes location 1FFE and is cleared when left port reads location
7C144-15
7C145-15
220
15
60
Description
7C144-25
180
25
40
CY7C144 CY7C145
7C144-55
160
55
30
0
pin is used when writing
Page 4 of 23
Unit
mA
mA
ns
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