CY7C1371D-133AXCT Cypress Semiconductor Corp, CY7C1371D-133AXCT Datasheet - Page 23

• Manufacturer Part Number: CY7C1371D-133AXCT
• Description: CY7C1371D-133AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1371D-133AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05556 Rev. *I
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
20. Timing reference level is 1.5 V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
23. t
24. At any voltage and temperature, t
25. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
Parameter
can be initiated.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve high Z prior to low Z under the same system conditions.
CHZ
, t
[22]
CLZ
, t
OELZ
, and t
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BW
CEN setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[20, 21]
X
X
setup before CLK rise
hold after CLK rise
OEHZ
[23, 24, 25]
DDQ
[23, 24, 25]
is less than t
= 3.3 V and is 1.25 V when V
POWER
Description
is the time that the power needs to be supplied above V
[23, 24, 25]
OELZ
[23, 24, 25]
and t
CHZ
is less than t
DDQ
= 2.5 V.
CLZ
to eliminate bus contention between SRAMs when sharing the same data
Min
7.5
2.1
2.1
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
133 MHz
Max
DD
6.5
4.0
3.2
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(minimum) initially, before a read or write operation
Min
2.5
2.5
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
–
–
0
–
100 MHz
Max
8.5
5.0
3.8
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1371D
CY7C1373D
Page 23 of 33
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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