CY7C1315KV18-250BZC Cypress Semiconductor Corp, CY7C1315KV18-250BZC Datasheet - Page 21

• Manufacturer Part Number: CY7C1315KV18-250BZC
• Description: CY7C1315KV18-250BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315KV18-250BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Power Up Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■
■
Document Number: 001-58904 Rev. *C
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐
❐
❐
Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Apply V
Apply V
Drive DOFF HIGH.
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
.
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
Figure 3. Power Up Waveforms
/
V
REF
DDQ
.
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
PLL Constraints
■
■
■
DDQ
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The PLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
Fix HIGH (or tie to V DDQ )
> 20 s Stable clock
Stable)
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
Start Normal
Operation
KC Var
Page 21 of 33
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