CY7C0853V-133BBXI Cypress Semiconductor Corp, CY7C0853V-133BBXI Datasheet - Page 13

• Manufacturer Part Number: CY7C0853V-133BBXI
• Description: CY7C0853V-133BBXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-133BBXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 172-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C0850AV / CY7C0851V / CY7C0851AV / CY7C0852V
/CY7C0852AV / CY7C0853V / CY7C0853AV incorporates an
IEEE 1149.1 serial boundary scan test access port (TAP). The
TAP controller functions in a manner that does not conflict with
the operation of other devices using 1149.1-compliant TAPs. The
TAP operates using JEDEC-standard 3.3 V I/O logic levels. It is
composed of three input connections and one output connection
required by the test logic defined by the standard.
Table 4. Identification Register Definitions
Table 5. Scan Registers Sizes
Table 6. Instruction Identification Codes
Notes
Document #: 38-06070 Rev. *J
Revision number (31:28)
Cypress device ID (27:12)
Cypress JEDEC ID (11:1)
ID register presence (0)
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
17. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
18. See details in the device BSDL files.
Instruction
Instruction Field
Register Name
Boundary Scan
All other codes Other combinations are reserved. Do not use other than the above.
Identification
Instruction
Bypass
Code
0000
0100
1000
1011
0111
1100
1111
C001h
C002h
C092h
Value
034h
0h
1
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/
CY7C0853AV output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
Reserved for version number.
Defines Cypress part number for the CY7C0851V/0851AV
Defines Cypress part number for the CY7C0852V/0852AV and
CY7C0853V/0853AV
Defines Cypress part number for the CY7C0850AV
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
[17]
CY7C0850AV,CY7C0851V/CY7C0851AV
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are operating.
An MRST must be performed on the devices after power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Description
Description
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Bit Size
n
32
[18]
4
1
DD
) for five rising
Page 13 of 36
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