CY7C0851AV-133BBI Cypress Semiconductor Corp, CY7C0851AV-133BBI Datasheet - Page 19

• Manufacturer Part Number: CY7C0851AV-133BBI
• Description: CY7C0851AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0851AV-133BBI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 2M (64K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 172-LFBGA
• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Word Size: 36b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06070 Rev. *J
31. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV
32. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
33. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
35. CE
36. CE
device from this data sheet. ADDRESS
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
ADDRESS
ADDRESS
0
DATA
DATA
0
= B0 – B3 = R/W = LOW; CE
= OE = B0 – B3 = LOW; CE
ADDRESS
OUT(B2)
DATA
OUT(B1)
CE
CE
DATA
CLK
(B1)
(B1)
(B2)
(B2)
CLK
R/W
OUT
CE
IN
t
t
t
t
SC
SC
SA
SA
t
t
t
SW
SC
SA
A
A
A
0
0
1
1
n
t
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
= R/W = CNTRST = MRST = HIGH.
CH2
t
CH2
(continued)
Figure 11. Read-to-Write-to-Read (OE = LOW)
(B1)
t
t
t
t
t
t
CYC2
HC
HC
CYC2
t
HA
HA
t
t
HW
HC
HA
= ADDRESS
t
t
CL2
CL2
A
A
READ
A
n+1
1
1
t
CD2
Figure 10. Bank Select Read
(B2)
t
CD2
.
t
SW
t
SC
Q
n
Q
t
0
SC
A
n+2
A
t
A
CKHZ
NO OPERATION
2
2
t
t
DC
HC
t
CY7C0850AV,CY7C0851V/CY7C0851AV
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
HD
[31, 32]
A
A
1
3
3
t
DC
t
t
CKLZ
CKHZ
WRITE
t
[30, 33, 34, 35, 36]
CD2
t
CKLZ
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
A
n+3
t
CD2
A
Q
A
4
4
2
t
t
t
CKHZ
CD2
CKLZ
READ
Q
n+1
A
Q
n+4
3
t
CD2
A
A
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
n+3
Page 19 of 36
Q
4
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