CY62128EV30LL-45ZXIT Cypress Semiconductor Corp, CY62128EV30LL-45ZXIT Datasheet

CY62128EV30LL-45ZXIT

CY62128EV30LL-45ZXIT

Manufacturer Part Number
CY62128EV30LL-45ZXIT
Description
CY62128EV30LL-45ZXIT
Manufacturer
Cypress Semiconductor Corp

Specifications of CY62128EV30LL-45ZXIT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (128K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TSOP I
Density
1Mb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3V
Address Bus
17b
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
16mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62128EV30LL-45ZXIT
Manufacturer:
CRYSTAL
Quantity:
1 408
Part Number:
CY62128EV30LL-45ZXIT
Quantity:
2 009
Part Number:
CY62128EV30LL-45ZXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
1-Mbit (128 K × 8) Static RAM
Features
Cypress Semiconductor Corporation
Document #: 38-05579 Rev. *J
Logic Block Diagram
Very high speed: 45 ns
Temperature ranges:
Wide voltage range: 2.2 V to 3.6 V
Pin compatible with CY62128DV30
Ultra low standby power
Ultra low active power
Easy memory expansion with CE
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Offered in Pb-free 32-pin SOIC, 32-pin thin small outline
package (TSOP) Type I, and 32-pin shrunk thin small outline
package (STSOP) packages
Industrial: –40 °C to +85 °C
Typical standby current: 1 µA
Maximum standby current: 4 µA
Typical active current: 1.3 mA at f = 1 MHz
CE 2
CE 1
WE
OE
1
, CE
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 10
A 11
A 9
2,
and OE features
198 Champion Court
COLUMN DECODER
INPUT BUFFER
128K x 8
ARRAY
Functional Description
The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
eight input and output pins (I/O
high impedance state when the device is deselected (CE
or CE
operation is in progress (CE
LOW).
To write to the device, take chip enable (CE
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A
To read from the device, take chip enable (CE
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
1-Mbit (128 K × 8) Static RAM
0
POWER
DOWN
through A
2
LOW), the outputs are disabled (OE HIGH), or a write
San Jose
16
).
,
CA 95134-1709
CY62128EV30 MoBL
1
LOW and CE
0
through I/O
1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
HIGH or CE
Revised June 25, 2011
7
2
) are placed in a
1
1
HIGH and WE
LOW and CE
LOW and CE
408-943-2600
®
2
) in portable
LOW). The
1
HIGH
®
2
2
[+] Feedback

Related parts for CY62128EV30LL-45ZXIT

CY62128EV30LL-45ZXIT Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-05579 Rev. *J 1-Mbit (128 K × 8) Static RAM Functional Description The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL applications such as cellular telephones ...

Page 2

Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 ...

Page 3

... Product Portfolio Product Range V CC Min CY62128EV30LL Industrial 2.2 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05579 Rev. *J [1] Figure 2. 32-pin TSOP I ...

Page 4

... Document #: 38-05579 Rev input voltage Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch-up current .................................................... > 200 mA Operating Range + 0.3 V Device CC(max) CY62128EV30LL Industrial –40 °C to +85 ° 0.3 V CC(max) Test Conditions I = –0 –1.0 mA, V > 2. ...

Page 5

Capacitance [8] Parameter Description C Input capacitance IN C Output capacitance OUT Thermal Resistance [8] Parameter Description  Thermal resistance JA (junction to ambient)  Thermal resistance JC (junction to case) AC Test Loads and Waveforms OUTPUT ...

Page 6

Data Retention Characteristics Over the Operating Range Parameter Description V V for data retention DR CC [10] I Data retention current CCDR [11] t Chip deselect to data retention CDR time [12] t Operation recovery time R Data Retention Waveform ...

Page 7

Switching Characteristics Over the Operating Range [14, 15] Parameter Read Cycle t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW to data valid ACE t OE LOW to ...

Page 8

Switching Waveforms Figure 6. Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) 2 ADDRESS CE t ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE t V ...

Page 9

Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled) ADDRESS DATA I/O NOTE 28 t HZOE Figure 9. Write Cycle No. 2 (CE ADDRESS CE WE DATA I/O Notes 24. The internal write ...

Page 10

Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 31 DATA I/O t HZWE Notes 29 the logical combination of CE and CE . When ...

Page 11

Truth Table [32 [32 Note 32. The ‘X’ (Don’t care) state for the Chip ...

Page 12

... Ordering Information Speed Ordering Code (ns) 45 CY62128EV30LL-45SXI CY62128EV30LL-45ZXI CY62128EV30LL-45ZAXI Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions 621 V30 LL Document #: 38-05579 Rev. *J Package Package Type Diagram 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) ...

Page 13

Package Diagrams Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 Document #: 38-05579 Rev. *J ® CY62128EV30 MoBL 51-85081 *C Page [+] Feedback ...

Page 14

Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056 Document #: 38-05579 Rev. *J ® CY62128EV30 MoBL 51-85056 *F Page [+] Feedback ...

Page 15

Package Diagrams (continued) Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 Document #: 38-05579 Rev. *J ® CY62128EV30 MoBL 51-85094 *F Page [+] Feedback ...

Page 16

Acronyms Acronym Description BHE byte high enable BLE byte low enable CE chip enable CMOS complementary metal oxide semiconductor I/O input/output OE output enable SOIC small outline integrated circuit SRAM static random access memory STSOP shrunk thin small outline package ...

Page 17

... Changed the Maximum rating of Ambient Temperature with Power Applied from 55°C to +125°C to –55°C to +125°C. Corrected “t ” spec description in the “Switching Characteristics” table. PD VKN Included “CY62128EV30LL-45ZAXA” part in the Ordering Information table VKN Added footnote #21 related to chip enable Updated package diagrams Updated template AJU ...

Page 18

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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