CS8422-CNZR Cirrus Logic Inc, CS8422-CNZR Datasheet - Page 10

• Manufacturer Part Number: CS8422-CNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

10
Pin Name
XTI
XTO
ILRCK
ISCLK
SDIN
GPO[3:0]
V_REG
VD_FILT
DGND
VL
SDOUT2
OSCLK2
OLRCK2
TDM_IN
SDOUT1
OSCLK1
OLRCK1
RMCK
RST
THERMAL PAD
Pin #
12
13
14
15
16
17
18
30
19
20
21
22
23
24
25
26
27
28
29
31
32
11
-
Pin Description
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See
Clock” on page 38
Crystal Out (Output) - Crystal output for Master clock. See
more details.
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDIN pin.
Serial Audio Input Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Data Port (Input) - Audio data serial input pin.
General Purpose Outputs (Output) - See
to VL on GPO2 will set AD2 chip address bit to 1, otherwise AD2 will be 0.
Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V.
Digital Voltage Regulator (Output) - Digital core voltage regulator output. Should be connected to
digital ground through a 10 µF capacitor. Typically +2.5 V. Cannot be used as an external voltage
source.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
Logic Power (Input) - Input/Output power supply, typically +1.8 V, +2.5 V, +3.3 V, or +5.0 V.
Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin.
Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2
pin.
Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT2 pin.
Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input.
Should remain grounded when not used. See
page
Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin.
Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT 1
pin.
Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT 1 pin.
Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128x,
192x, 256x, 384x, 512x, 768x, or 1024x Fs, where Fs is the sample rate of the incoming AES3-
compatible data, or ISCLK/64.
Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are
reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dis-
sipation.
27.
for more details.
page 50
“Time Division Multiplexing (TDM) Mode” on
for details. In I²C Mode, a 20 kΩ pull-up resistor
“SRC Master Clock” on page 38
“SRC Master
CS8422
DS692PP1
for