CS8420-DSZR Cirrus Logic Inc, CS8420-DSZR Datasheet - Page 9

• Manufacturer Part Number: CS8420-DSZR
• Description: IC,Digital Audio Sample Rate Converter,SOP,28PIN
• Manufacturer: Cirrus Logic Inc

DS245F4
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
Slave Mode
I/OSCLK Period
I/OSCLK Input Low Width
I/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
I/OLRCK Edge Setup Before I/OSCLK Active Edge
OSCLK
(output)
O LRCK
(output)
(output)
(output)
O M CK
ISCLK
ILRCK
RM CK
RM CK
(input)
7. The active edges of ISCLK and OSCLK are programmable.
8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
9. The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
Figure 1. Audio Port Master Mode Timing
When these signals are derived from RMCK, they are clocked from its falling edge.
has changed.
Hardware M ode
Software M ode
t sm d
Parameter
t
lm d
L
= 20 pF.
(Note 7, 9, 12)
(Note 7, 9, 11)
(Note 7, 8)
(Note 10)
(Note 7)
(Note 7)
(Note 7)
(Note 9)
OLRCK
OSCLK
SDOUT
ILRCK
ISCLK
(input)
(input)
SDIN
Figure 2. Audio Port Slave Mode and Data Input Timing
Symbol
t
t
t
t
t
t
t
t
sckw
sckh
lrckd
lrcks
smd
t
t
sckl
dpd
lmd
t lrckd
dh
ds
Min
20
20
36
14
14
20
20
t
0
0
-
-
lrcks
t
ds
Typ
50
-
-
-
-
-
-
-
-
-
-
t sckh
t
dh
Max
25
16
17
-
-
-
-
-
-
-
-
t sckw
t sckl
CS8420
t dpd
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
9