CS8420-DSZR Cirrus Logic Inc, CS8420-DSZR Datasheet - Page 58

• Manufacturer Part Number: CS8420-DSZR
• Description: IC,Digital Audio Sample Rate Converter,SOP,28PIN
• Manufacturer: Cirrus Logic Inc

CS8420
RERR - Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per
sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding
error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
EMPH/U - Pre-Emphasis Indicator Output or U-Bit Data Input
The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type data stream,
or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When indicating emphasis,
EMPH/U is low if the incoming data indicates 50/15 μs pre-emphasis and high otherwise.
COPY - Copy Channel Status Bit Output
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is
also a start-up option pin, and requires a pull-up or pull-down resistor.
ORIG - Original Channel Status Output
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates
that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original.
PRO/C - Professional Channel Status Bit Output or C-Bit Data Input
The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type
data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK.
AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input
The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data
stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
OSCLK - Serial Audio Output Port Bit Clock Input or Output
Serial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at
all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current
transmitted sub-frame to be the start of a channel status block.
TCBLD - Transmit Channel Status Block Direction Input
Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input.
TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset
state.
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