CS61584A-IQ3Z Cirrus Logic Inc, CS61584A-IQ3Z Datasheet - Page 24

• Manufacturer Part Number: CS61584A-IQ3Z
• Description: IC,Line Interface,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ3Z

• Interface: Parallel/Serial
• Voltage - Supply: 3.3V, 5V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1713

24
Latched-LOS: Set high on the rising edge of the
loss of signal condition. Reading the Status register
clears the Latched-LOS bit and deactivates the INT
pin. Refer to the timing diagram in Figure 18.
AIS: Set high while the alarm indication signal is
detected. Reading the Status register does not clear
24
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
(AIS/LOS bit & AIS/LOS pin)
AIS/LOS Currently Active
LOS1
Latched-LOS1
AIS1
Latched-AIS1
Latched-BPV1
Latched-Overflow1 Pulse overflow since last read
Latched-Reset
Interrupt1
LOS2
Latched-LOS2
AIS2
Latched-AIS2
Latched-BPV2
Latched-Overflow2 Pulse overflow since last read
Latched-CLKLOST TCLK or REFCLK absent
Interrupt2
Read AIS/LOS bits
Description
Description
(Latch AIS/LOS bit)
Latched LOS
Interrupt
(INT)
Serial Port Address: 0x10; Parallel Port Address: 0xY0
Serial Port Address: 0x11; Parallel Port Address: 0xY1
LOS currently detected
LOS event since last read
AIS currently detected
AIS event since last read
BPV event since last read
Reset event since last read
Interrupt event since last read
LOS currently detected
LOS event since last read
AIS currently detected
AIS event since last read
BPV event since last read
Interrupt event since last read
Figure 18. Alarm Indication Event Relationships
Set by Change
of AIS/LOS
Set by start
of AIS/LOS
"Short" AIS/LOS event
Status Register (Channel 1)
Status Register (Channel 2)
Table 5. Status Registers
1
1
DS261PP5
Cleared by read
Cleared by read
the AIS bit. An AIS interrupt is generated only on
the falling edge of the AIS alarm condition. The
Latched-AIS bit generates an interrupt on the rising
edge of AIS. Refer to the timing diagram in
Figure 18.
Definition
Definition
no LOS
no LOS
no AIS
no AIS
no BPV
no overflow
no reset
no interrupt
no LOS
no LOS
no AIS
no AIS
no BPV
no overflow
TCLK and REFCLK present
no interrupt
"Long" AIS/LOS event
0
0
CS61584A
CS61584A
DS261PP5
Reset
Reset
DS261F1
Value
Value
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0