CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet - Page 24

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CS5376A-IQZ

Manufacturer Part Number
CS5376A-IQZ
Description
IC,Digital Filter,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5376A-IQZ

Filter Type
Digital
Number Of Filters
4
Max-order
2nd
Voltage - Supply
3 V ~ 5 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Operating Temperature
-40 to 85 °C
Resolution (bits)
24bit
Conversion Rate
4kSPS
Operating Temperature Range
-40°C To +85°C
No. Of Pins
64
Msl
MSL 3 - 168 Hours
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1778 - EVALUATION BOARD FOR CS5376
Frequency - Cutoff Or Center
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5376A-IQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS5376A-IQZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS5376A-IQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
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6. CLOCK GENERATION
The CS5376A requires a 32.768 MHz master clock
input, which is used to generate internal digital fil-
ter clocks and external modulator clocks.
6.1 Pin Description
CLK - Pin 58
Clock input, nominal frequency 32.768 MHz.
6.2 Synchronous Clocking
To guarantee synchronous measurements through-
out a sensor network, the CS5376A master clock
should be distributed to arrive at all nodes in phase.
The 32.768 MHz master clock can either be direct-
ly distributed through the system telemetry, or re-
constructed locally using a VCXO based PLL. To
24
CLK
Figure 12. Clock Generation Block Diagram
DSPCFG Register
Clock Divider
Generator
MCLK
and
ensure recovered clocks have identical phase, sys-
tem PLL designs should use a phase/frequency de-
tector architecture.
6.3 Master Clock Jitter and Skew
Care must be taken to minimize jitter and skew in
the received master clock as both parameters affect
measurement performance.
Jitter in the master clock causes jitter in the gener-
ated modulator clocks, resulting in sample timing
errors and increased noise.
Skew in the master clock from node to node creates
a sample timing offset, resulting in systematic mea-
surement errors in the reconstructed signal.
Internal
Clocks
MCLK
Output
CS5376A
DS612F4

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