CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet
CS5376A-IQZ
Specifications of CS5376A-IQZ
Available stocks
Related parts for CS5376A-IQZ
CS5376A-IQZ Summary of contents
Page 1
... CS4373A ∆Σ test DAC a synchronous, high-resolution, self-testing, multi-channel measurement system can be designed quickly and easily. Digital filter coefficients for the CS5376A FIR and IIR fil- ters are included on-chip for a simple setup, or they can be programmed for custom applications. Selectable dig- ...
Page 2
... Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 13 Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Power Consumption .14 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3. System Design with CS5376A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2. Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4. Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.5. System Configuration .20 3.6. Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.7. Data Collection .20 3 ...
Page 3
... Serial Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 16.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.2. SD Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 16.3. SD Port Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17. Test Bit Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.2. TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.3. TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 17.4. TBS Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 17.5. TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 17.6. TBS Loopback Testing .66 DS612F4 CS5376A 3 ...
Page 4
... Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27. Environmental, Manufacturing, & Handling Information . . . . . . 106 28. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LIST OF FIGURES Figure 1. CS5376A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 2. Digital Filtering Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 3. FIR and IIR Coefficient Set Selection Word .11 Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 5. MISO Read Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 6 ...
Page 5
... Figure 54. Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . .96 Figure 55. Test Bit Stream Configuration Register TBSCFG . . . . . . . . . . . . . . .97 Figure 56. Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . .98 Figure 57. User Defined System Register SYSTEM1 .99 Figure 58. Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . .100 Figure 59. Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . .101 DS612F4 CS5376A 5 ...
Page 6
... Table 13. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 14. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 15. FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 16. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 17. IIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 18. IIR Filter Coefficients .58 Table 19. TBS Configurations Using On-chip Data . . . . . . . . . . . . . . . . . . . . . .65 Table 20. JTAG Instructions and IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 21. JTAG Scan Cell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 DS612F4 CS5376A 6 ...
Page 7
... Serial Data Output Port JTAG Interface 1. GENERAL DESCRIPTION The CS5376A is a multi-channel digital filter with integrated system peripherals. Figure 1 illustrates a simplified block diagram of the CS5376A. 1.1 Digital Filter Features • Multi-channel decimation CS5371A/72A ∆Σ modulators channel concurrent operation. • Synchronous operation for simultaneous sam- pling in multi-sensor systems ...
Page 8
... Secondary SPI 2 serial port to control local serial peripherals. - JTAG port for boundary scan (IEEE 1149.1 compliant). 1.3 System Level Features • Flexible configuration options. - Configuration 'on-the-fly' via microcontrol- ler or system telemetry. - Fixed configuration via stand-alone boot EEPROM. • Low power consumption. CS5376A IIR2 nd 2 Order DS612F4 ...
Page 9
... Configuration commands written through Seri- al Peripheral Interface 1. (See Table 1) - Standardized microcontroller interface us- ing SPI 1 registers. (See Table 3) - Commands write digital filter registers, fil- ter coefficients, and test bit stream data. - Digital filter registers set hardware config- uration options. CS5376A 9 ...
Page 10
... Write Custom Test Bit Stream Data (TBS DATA Use On-Chip TBS Data 07 - Start Digital Filter Operation CS5376A Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients Use On-Chip Coefficients Write Custom Test Bit Stream Data ...
Page 11
... Table 2. TBS Configurations Using On-Chip Data CS5376A 7:4 3:0 FIR2 FIR1 Bits 3:0 FIR1 Coefficients 0000 Linear Phase 0001 Minimum Phase Bits 7:4 FIR2 Coefficients ...
Page 12
... Offset Correction Channel 4 R/W 24 Time Break Delay R/W 24 Test Bit Stream Configuration R/W 24 Test Bit Stream Gain R/W 24 User Defined System Register 1 R/W 24 User Defined System Register 2 R/W 24 Hardware Version ID R/W 24 Self-Test Result Code Table 3. SPI 1 and Digital Filter Registers CS5376A Description Description 12 ...
Page 13
... Storage Temperature Range 1. Transient currents up to 100 mA will not cause SCR latch-up. DS612F4 = 25°C. Symbol VDD1 VDD2 Industrial (-IQ) Symbol Logic Core Microcontroller Interface Modulator Interface (Note 1) (Note 1) (Note 1) CS5376A Min Nom Max VD 2.85 3.0 5.25 3.135 3.3 5.25 3.135 3.3 5.25 T ...
Page 14
... RISE t FALL t RISE t FALL (Note OUT t fa llin 0.9 * VDD 2.6 V 0.1 * VDD 0.7 V Symbol PWR 1 PWR 2 PWR 4 PWR 8 PWR 16 PWR S CS5376A Min Typ Max - - 135 - 65 -40 - +85 Min Typ Max 0.6 * VDD - VDD 0.0 - 0.8 VDD - 0.3 - VDD 0 100 - - 100 - - ...
Page 15
... SCK1 Falling to New Data Bit SCK1 High Time SCK1 Low Time SSI Rising to MISO Hi-Z DS612F4 MSB - Figure 4. MOSI Write Timing in SPI Slave Mode MSB - Figure 5. MISO Read Timing in SPI Slave Mode Symbol CS5376A LSB LSB Min Typ Max 120 - - 3 120 - - 4 120 - - ...
Page 16
... Data Hold Time After SDCLK Rising SDCLK High Time SDCLK Low Time SDCLK Rising to SDRDY Rising Data Hold Time After SDRDY Rising SDRDY High to SDTKO Rising Edge SDTKO High Time DS612F4 Figure 6. SD Port Read Timing Symbol CS5376A Min Typ Max Unit 1000 120 - - ...
Page 17
... Synchronization after SYNC rising MSYNC Setup Time to MCLK rising MCLK rising to Valid MDATA MSYNC falling to MCLK rising Notes: 3. Master clock frequencies above or below 32.768 MHz will affect generated clock frequencies. 4. Sampling synchronization between multiple CS5376A devices receiving identical SYNC signals. DS612F4 t msh t ...
Page 18
... TBSCLK phase can be delayed in 1/8 increments. The timing diagram shows no TBSCLK delay. 6. TBSDATA can be delayed from full bit periods. The timing diagram shows no TBSDATA delay. DS612F4 Figure 8. TBS Output Clock and Data Timing Symbol t 1 (Note (Note CS5376A t 5 Min Typ Max Unit µs - 3.906 - 256 - kbps 60 - ...
Page 19
... Power Supplies The multi-channel system shown in Figure 9 typi- cally operates from a and a 3.3 V digital power supply. The CS5376A logic core can be powered from minimize power consumption, if required. 3.2 Reset Control System reset is required only for the CS5376A de- ...
Page 20
... General Purpose I/O (GPIO) Twelve general purpose pins are available on the CS5376A for system control. Each pin can be set as input or output, high or low, with an internal pull- up enabled or disabled. The CS3301A/02A, CS5371A/72A and CS4373A devices in Figure 9 are configured by simple pin settings controlled through the CS5376A GPIO pins ...
Page 21
... MSYNC MDATA4 MFLAG4 4. POWER SUPPLIES The CS5376A has three sets of power supply in- puts. Two sets supply power to the I/O pins of the device (VDD1, VDD2), and the third supplies power to the logic core (VD). The I/O pin power supplies determine the maximum input and output ...
Page 22
... VD, GND - Pins 7, 40, 6, 23, 39 Sets the operational voltage of the CS5376A logic core. Can be driven with voltages from supply minimizes total power consumption. 4.2 Bypass Capacitors Each power supply pin should be bypassed with parallel 1 µF and 0.01 µF caps single 0.1 µF cap, placed as close as possible to the CS5376A ...
Page 23
... By EEPROM’ section of this data sheet, starting on page 26. Microcontroller Boot Fail When the BOOT pin is low after reset, the Code CS5376A enters an idle state waiting for a micro- 0x00000F controller to write configuration commands and 0x0000F0 initialize filter operation. Configuration commands 0x000F00 and data are written as specified in the ‘ ...
Page 24
... CLK 6. CLOCK GENERATION The CS5376A requires a 32.768 MHz master clock input, which is used to generate internal digital fil- ter clocks and external modulator clocks. 6.1 Pin Description CLK - Pin 58 Clock input, nominal frequency 32.768 MHz. 6.2 Synchronous Clocking To guarantee synchronous measurements through- out a sensor network, the CS5376A master clock should be distributed to arrive at all nodes in phase ...
Page 25
... The CS5376A has a dedicated SYNC input that aligns the internal digital filter phase and generates an external signal for synchronizing modulator an- alog sampling. By providing simultaneous rising edges to the SYNC pins of multiple CS5376A de- vices, synchronous sampling across a network can be guaranteed. 7.1 Pin Description SYNC - Pin 59 Synchronization input, rising edge triggered ...
Page 26
... Figure 14. EEPROM Configuration Block Diagram 8. CONFIGURATION BY EEPROM After reset, the CS5376A reads the state of the BOOT pin to determine a source for configuration commands. If BOOT is high, the CS5376A ini- tiates serial transactions through the SPI 1 port to read configuration information from an external EEPROM. 8.1 Pin Descriptions Pins required for EEPROM boot are listed here, other SPI 1 pins are inactive ...
Page 27
... Cycle SCK1 MSB MOSI MSB MISO EECS DS612F4 Address ADDR[15:0] Read data beginning at the address given in ADDR. READ 2 BYTE CMD ADDR 0x03 ADDR ADDR Figure 15. SPI 1 EEPROM Read Transactions CS5376A Definition DATA1 DATA2 DATA3 1 BYTE / 3 BYTE DATA LSB 2 1 LSB X 27 ...
Page 28
... The IIR co- efficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. See “IIR Filter” on page 55 for more information about IIR filter coefficients. CS5376A DS612F4 ...
Page 29
... NUM FIR2 (FIR COEF) 03 a11 Write Custom IIR Coefficients b10 b11 a21 a22 b20 b21 b22 04 COEF SEL Use On-Chip Coefficients 05 NUM TBS Write Custom Test Bit Stream Data (TBS DATA Use On-Chip TBS Data 07 - Start Digital Filter Operation CS5376A Description 29 ...
Page 30
... Measurement data becomes available one full sample period after this command is re- ceived. No data words are required for this EE- PROM command. Sample Command: 07 8.5 Example EEPROM Configuration Table 6 shows an example EEPROM file for a min- imal CS5376A configuration. CS5376A DS612F4 ...
Page 31
... Addr Data Description 00 00 Mfg header Write ROM Coefficients Write TBS ROM Data 15 01 Write CONFIG Register Write FILTCFG Register DS612F4 Addr Data Write TBSCFG Register Write TBSGAIN Register Filter Start Table 6. Example EEPROM File CS5376A Description 31 ...
Page 32
... Microcontroller serial transactions require toggling the SSI pin as the CS5376A chip select and writing a serial clock to the SCK1 input. Serial data is input to the CS5376A on the MOSI pin, and output from the CS5376A on the MISO pin. 9.3 Microcontroller Serial Transactions Microcontroller configuration commands are writ- ten to the digital filter through the SPI 1 registers ...
Page 33
... MSB MISO SSI DS612F4 Address ADDR[7:0] Write SPI 1 registers beginning at the address in ADDR. ADDR[7:0] Read SPI 1 registers beginning at the address in ADDR. 0x02 ADDR Data1 0x03 ADDR Data1 Figure 18. Microcontroller Serial Transactions CS5376A Definition Data2 DataN Data2 DataN LSB 2 1 LSB X 33 ...
Page 34
... There must be a small delay between transactions for the CS5376A to process the incoming data. Three methods can be used to ensure the CS5376A is ready to receive the next configuration command. 1) Delay a fixed 1 ms period to guarantee enough time for the command to be completed. ...
Page 35
... DATA) 000007 - - 000008 - - 000009 - - CS5376A Description No Operation Write Digital Filter Register Read Digital Filter Register Write Custom FIR Coefficients Write Custom IIR Coefficients Use On-Chip Coefficients Write Custom Test Bit Stream Data Use On-Chip TBS Data Start Digital Filter Operation ...
Page 36
... The first data word sets the number of TBS data to be written and the remaining data words are the TBS data values. See “Test Bit Stream Generator” CS5376A DS612F4 ...
Page 37
... No data words are required for this configuration command. Sample Command Delay 1 ms, monitor SINT, or poll E2DREQ 9.5 Example Microcontroller Configuration Table 6 shows example microcontroller transac- tions for a minimal CS5376A configuration. CS5376A 37 ...
Page 38
... Delay 1ms, monitor SINT, or poll E2DREQ Delay 1ms, monitor SINT, or poll E2DREQ Delay 1ms, monitor SINT, or poll E2DREQ Table 8. Example Microcontroller Configuration CS5376A Description Write ROM coefficients Write ROM TBS Data Write CONFIG Register Write FILTCFG Register Write TBSCFG Register Write TBSGAIN Register ...
Page 39
... MFLAG[4:1] 512 kHz DC Offset & Gain Correction 10.MODULATOR INTERFACE The CS5376A performs digital filtering for up to four ∆Σ modulators. Signals from the modulators are connected through the modulator data interface (MDI). 10.1 Pin Descriptions MCLK, MCLK/2 - Pins 13, 12 Modulator clock outputs. Nominally 2.048 MHz and 1 ...
Page 40
... MFLAG signal is cleared. The MFLAG inputs are mapped to status bits in the SD port, and are associated with each sample when written. See “Serial Data Port” on page 61 for more information on the MFLAG error bits in the SD port status byte. CS5376A DS612F4 ...
Page 41
... DC Offset & Gain Correction 11.DIGITAL FILTER INITIALIZATION The CS5376A digital filter consists of three multi- stage sections: a three stage SINC filter, a two stage FIR filter, and a two stage IIR filter. To initialize the digital filter, FIR and IIR coeffi- cient sets are selected using configuration com- ...
Page 42
... Standby Mode The CS5376A can be placed in a low-power stand- by mode by sending the ‘Filter Stop’ configuration command and programming the digital filter clock to 32 kHz. In this mode the digital filter idles, con- suming minimal power until re-enabled by later configuration commands ...
Page 43
... The SINC filter is synchronized to the external sys- tem by the MSYNC signal, which is generated from the SYNC input. The MSYNC signal sets a reference time (time 0) for all filter operations, and the SINC filter is restarted to phase align with this reference time. CS5376A 4th order sinc2 stage4 2 2 ...
Page 44
... Deci- Stages mation mation 3 2,3 1,2,3 2,3 1,2,3 1,2,3 3 2,3 1,2,3 3 2,3 1,2,3 1,2,3,4 Table 9. SINC Filter Configurations CS5376A 6 coefficients 7 coefficients SINC3 SINC3 Deci- Stages mation 3,4,5 4 4,5 20 3,4,5 20 3,4,5 4 100 2,3,4,5 20 3,4,5 100 2,3,4,5 100 2,3,4,5 100 2,3,4,5 500 1,2,3,4,5 44 ...
Page 45
... − − 1 ⎝ ⎠ ⎛ ⎞ − − ⎜ ⎜ ⎟ ⎟ − − 1 ⎝ ⎠ Table 10. SINC1 and SINC2 Filter Coefficients CS5376A Filter Coefficients 2460 2380 2226 2010 1750 126 h = 1470 210 h = 1190 6 ...
Page 46
... − − 1 ⎝ ⎠ ⎛ ⎞ − − ⎜ ⎜ ⎟ ⎟ − − 1 ⎝ ⎠ ⎛ ⎞ − − ⎜ ⎜ ⎟ ⎟ − − 1 ⎝ ⎠ Table 11. SINC3 Filter Coefficients CS5376A = 126 = 141 = 126 = ...
Page 47
... Figure 26 and Table 12. Which on-chip coefficient set to use is selected by a data word following the ‘Write ROM Coeffi- cients’ configuration command. See “Filter Coeffi- cient Selection” on page 41 for information about selecting on-chip coefficient sets. CS5376A 47 ...
Page 48
... Custom filter sets should normalize the maximum coefficient value to 24-bit two’s complement full scale, 0x7FFFFF, and scale all other coefficients accordingly. To maintain maximum internal dy- namic range, the CS5376A FIR filter performs double precision calculations with an automatic gain correction to scale the final output. 48 Custom FIR coefficients are uploaded using the ‘ ...
Page 49
... Table 12. FIR Filter Characteristics CS5376A Passband Stopband Ripple Atten- ( ± dB) uation (dB) 0.0042 130.38 0.0045 130.38 0.0040 130.42 0.0041 130.42 0.0080 130.45 0.0064 130.43 0.0041 130.43 ...
Page 50
... Table 13. SINC + FIR Group Delay CS5376A Group Delay (Filter Stage Input Rate) 36 17.5 7 3.0 8.5 19.0 40.0 13 6.0 7 3.0 8.5 50.5 260.5 1310 ...
Page 51
... Minimum phase group delay FIR1 Minimum Phase Group Delay (Normalized frequency) FIR2 Minimum Phase Group Delay (Normalized frequency) DS612F4 Figure 27. Minimum Phase Group Delay CS5376A 51 ...
Page 52
... Table 14. FIR1 Coefficients CS5376A h = 8388607 7042723 4768946 2266428 189436 -1053303 -1392827 -1084130 -496361 39864 332367 375562 258881 97434 -19450 -69909 -67365 -39787 -14518 ...
Page 53
... Table 15. FIR2 Linear Phase Coefficients CS5376A h = 8388607 3875315 -766230 -1854336 -137179 1113788 454990 -642475 -553873 298975 533334 -49958 -443272 -116005 318763 208018 -187141 -238025 ...
Page 54
... Table 16. FIR2 Minimum Phase Coefficients CS5376A h = 67863 -190800 -128546 114197 147750 -46352 -143269 -13290 114721 51933 -75952 -68746 38171 68492 -7856 -57526 -12540 41717 ...
Page 55
... The characteristic equations for the 2nd order IIR include an input value output value, Y, and three intermediate values, W3, W4, and W5, each separated by a delay element (z CS5376A ...
Page 56
... Custom filter sets should normalize the coefficients to 24-bit two’s complement full scale, 0x7FFFFF. To maintain maximum internal dynamic range, the CS5376A IIR filter performs double precision calculations with an automatic gain correction to scale the final output. Custom IIR coefficients are uploaded using the ‘ ...
Page 57
... IIR2 Coeff IIR2 Selection Corner Frequency 0 0.15 0.30 0.60 0.90 1.20 Table 17. IIR Filter Characteristics CS5376A ( 2000 SPS 1000 SPS 500 SPS 333 SPS 250 SPS 2000 SPS 1000 SPS 500 SPS 333 SPS 250 SPS 2000 SPS 1000 SPS 500 SPS) ...
Page 58
... ⎜ − − ⎝ Table 18. IIR Filter Coefficients CS5376A Filter Coefficients (normalized 24-bit -8309916 8349262 -8349262 -8231957 8310282 -8310282 -8078179 8233393 -8233393 -7927166 8157887 -8157887 -7778820 8083714 -8083714 11 Filter Coefficients (normalized 24-bit) ⎞ a ...
Page 59
... Unity Gain: GAIN = 0x7FFFFF 50% Gain: GAIN = 0x3FFFFF Zero Gain: GAIN = 0x000000 Once the GAIN registers are written, the USEGR bit in the FILTCFG register enables gain correc- tion. 15.2 Offset Correction Offset correction in the CS5376A cancels the DC bias of a measurement channel by subtracting the CS5376A 59 ...
Page 60
... Once the OFFSET registers are written, the USE- OR bit in the FILTCFG register enables offset cor- rection. 15.3 Offset Calibration An offset calibration algorithm in the CS5376A can automatically calculate offset correction val- ues. When using the offset calibration algorithm, background noise data should be used as the basis for calculating the offset value of each measure- ment channel ...
Page 61
... Time Break Bit - TB The time break bit marks a timing reference based on a rising edge into the TIMEB pin. After a pro- grammed delay, the TB bit in the status byte is set for one output sample in all channels. The TIME- CS5376A CS5376A SDTKI SDRDY SDCLK SDDAT SDTKO ...
Page 62
... A rising edge into SDTKI when new data is available in the SD port FIFO causes the CS5376A to initiate an SD port transaction by driving SDRDY low. If data is not yet available in the SD port FIFO, the SDTKI sig- nal is passed through to the SDTKO output ...
Page 63
... SD port FIFO DS612F4 MSB Figure 33. SD Port Transaction causes the CS5376A to initiate an SD port transac- tion by driving SDRDY low. If data is not available in the SD port FIFO, the SDTKI signal is passed through to the SDTKO output. Once an SD port transaction is initiated, serial clocks into SDCLK cause data to be output to SDDAT, as shown in Figure 33 ...
Page 64
... Figure 34. Test Bit Stream Generator Block Diagram 17.TEST BIT STREAM GENERATOR The CS5376A test bit stream (TBS) generator cre- ates sine wave ∆Σ bit stream data to drive an exter- nal test DAC. The TBS digital output can also be internally connected to the MDATA inputs for loopback testing of the digital filter ...
Page 65
... TBS data. TBS ROM Data An on-chip 24-bit 1024 point digital sine wave is stored on the CS5376A. When selected by the ‘Write TBS ROM Data’ configuration command, the TBS generator can produce the test signal fre- quencies listed in Table 19. Additional discrete test ...
Page 66
... When the TSYNC bit is set in the TBSCFG regis- ter, the MSYNC signal resets the sine wave data pointer and phase aligns the TBS signal output. Once the digital filter is settled, all CS5376A de- vices receiving the SYNC signal will have identical TBS signal phase. See “Synchronization” on ...
Page 67
... Step Input and Group Delay A simple method to empirically measure the step response and group delay of a CS5376A measure- ment channel is to use the time break signal as both a timing reference input and an analog step input. ...
Page 68
... SPI 2 serial ports. Figure 36 shows the structure of a bi-directional GPIO pin with SPI chip select func- tionality. When the CS5376A is used as an SPI master, either when booting from EEPROM using SPI 1 or per- forming master mode transactions using SPI 2, the chip select signals from SPI 1 and SPI 2 are logi- cally AND-ed with the GPIO data bit ...
Page 69
... Similarly output pin is writ- ten as a logical 0 but forced high externally, the read value reflects the pin state and returns a logical 1. In both cases the CS5376A is in contention with the external device resulting in increased power consumption. CS5376A ...
Page 70
... The Serial Peripheral Interface 2 (SPI 2) port is a master mode SPI port designed to interface with se- rial peripherals. By writing the SPI2 digital filter registers, multiple serial slave devices can be con- trolled through the CS5376A. 20.1 Pin Descriptions CS[4:0] - Pins Serial chip selects. Multiplexed with GPIO pins. ...
Page 71
... The SPI2CMD register (0x11 16-bit digital fil- ter register with the high byte designated as an SPI command and the low byte designated as an ad- dress. The high byte holds an 8-bit SPI ‘write’ or ‘read’ opcode, as shown in Figure 38, and the low byte holds an 8-bit serial address. CS5376A 71 ...
Page 72
... SCK2 latches valid data. In SPI mode 3, the SCK2 serial clock is defined ini- tially in a high state. Output data on the SO pin is invalid until the initial falling edge of SCK2, and the first rising edge of SCK2 latches valid data. CS5376A DS612F4 ...
Page 73
... SPI2CMD[7:0] Write serial peripheral beginning at the address given in SPI2CMD[7:0]. SPI2CMD[7:0] Read serial peripheral beginning at the address given in SPI2CMD[7:0]. SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT 0x02 ADDR Data1 SPI2CMD[15:8] SPI2CMD[7:0] 0x03 ADDR Data1 SPI2DAT Figure 38. SPI 2 Master Mode Transactions CS5376A Definition Data2 Data3 Data2 Data3 73 ...
Page 74
... Slave devices only drive SI after being selected and responding to a read command. CS SPI 2 Transaction with SCKPH=1 Cycle SCK2 SCKPO = 0 SCK2 SCKPO = Slave devices only drive SI after being selected and responding to a read command. CS DS612F4 MSB MSB Figure 39. SPI 2 Transaction Details CS5376A LSB 2 1 LSB LSB LSB 74 ...
Page 75
... Serial output from the scan chain or TAP controller. 21.2 JTAG Architecture The JTAG test circuitry consists of a test access port (TAP) controller and boundary scan cells connected to each pin. The boundary scan cells are linked together to create a scan chain around the CS5376A. DS612F4 TAP ...
Page 76
... IEEE 1149.1 specifica- tion, which are sequenced using TMS and TCK. 21.2.3 Boundary Scan Cells The CS5376A JTAG test port provides access to all device pins via internal boundary scan cells. When the JTAG port is disabled, boundary scan cells are transparent and do not affect CS5376A operation ...
Page 77
... GPIO9 data in 61 data out 62 output enable 63 pullup 64 GPIO10 data in 65 data out 66 output enable 67 pullup Table 21. JTAG Scan Cell Mapping CS5376A BRC Pin Function 68 GPIO11 data in 69 data out 70 output enable 71 pullup 72 SSO data out 73 output enable 74 WOM 75 SCK1 ...
Page 78
... REVISION HISTORY The CS5376A is a pin compatible upgrade to the CS5376. The part family has had three revisions: CS5376 rev A CS5376 rev B CS5376A rev A The part number change for CS5376A reflects ad- ditional functionality built into the device. 22.1 Changes from CS5376 rev A to ...
Page 79
... Modified Test Bit Stream (TBS) to disable loopback when TBS disabled. If TBS loopback mode was enabled, the exter- nal MDATA inputs were disconnected from the SINC filter even if the TBS was disabled. Now when the TBS is disabled, loopback mode is automatically disabled also. CS5376A 79 ...
Page 80
... TIMEBREAK register (0x29) disabled the TIMEB status bit write, and a '1' value set the status bit in the current output word. Now, a '0' value sets the TIMEB status bit in the current output word, and a '1' value delays until the fol- lowing word. CS5376A DS612F4 ...
Page 81
... SUMMARY 23.1 SPI 1 Registers The CS5376A SPI 1 registers interface the serial port to the digital filter. Name Addr. SPI1CTRLH 00 SPI1CTRLM 01 SPI1CTRLL 02 SPI1CMDH 03 SPI1CMDM 04 SPI1CMDL 05 SPI1DAT1H 06 SPI1DAT1M 07 SPI1DAT1L 08 SPI1DAT2H 09 SPI1DAT2M 0A SPI1DAT2L 0B DS612F4 Type # Bits R/W 8 SPI 1 Control Register, High Byte R/W 8 SPI 1 Control Register, Middle Byte ...
Page 82
... SPI 1 mode fault flag 7:0 14:13 -- reserved 12 EMOP External master to SPI 1 operation in progress flag 11 SWEF SPI 1 write collision error flag 10:9 -- reserved 8 E2DREQ External master to digital filter request flag CS5376A 16 SPI 1 Address: 0x00 -- 0x01 R/W 0x02 1 -- Not defined; read Readable E2DREQ W Writable R/W R/W ...
Page 83
... R/W R/W R S1CMD4 S1CMD3 S1CMD2 S1CMD1 R/W R/W R/W R 15:8 S1CMD[15:8] SPI 1 Command Middle Byte CS5376A 16 SPI 1 Address: 0x03 S1CMD16 0x04 0x05 R Not defined; read Readable S1CMD8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows S1CMD0 are reset condition ...
Page 84
... R/W R/W R S1DAT4 S1DAT3 S1DAT2 S1DAT1 R/W R/W R/W R 15:8 S1DAT[15:8] SPI 1 Data Middle Byte CS5376A 16 SPI 1 Address: 0x06 S1DAT16 0x07 0x08 R Not defined; read Readable S1DAT8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows S1DAT0 are reset condition ...
Page 85
... R/W R/W R S1DAT4 S1DAT3 S1DAT2 S1DAT1 R/W R/W R/W R 15:8 S1DAT[15:8] SPI 1 Data Middle Byte CS5376A 16 SPI 1 Address: 0x09 S1DAT16 0x0A 0x0B R Not defined; read Readable S1DAT8 W Writable R/W R/W Readable and 0 Writable (LSB) 0 Bits in bottom rows S1DAT0 are reset condition ...
Page 86
... Digital Filter Registers The CS5376A digital filter registers control hardware peripherals and filtering functions. Name Addr. CONFIG 00 RESERVED 01-0D GPCFG0 0E GPCFG1 0F SPI2CTRL 10 SPI2CMD 11 SPI2DAT 12 RESERVED 13-1F FILTCFG 20 GAIN1 21 GAIN2 22 GAIN3 23 GAIN4 24 OFFSET1 25 OFFSET2 26 OFFSET3 27 OFFSET4 28 TIMEBRK 29 TBSCFG 2A TBSGAIN 2B SYSTEM1 2C SYSTEM2 ...
Page 87
... MCKFS MCLK frequency select [2:0] 111: reserved 110: reserved 101: 4.096 MHz 100: 2.048 MHz 011: 1.024 MHz 010: 512 kHz 001: reserved 000: reserved CS5376A 16 DF Address: 0x00 DFS0 R/W -- Not defined; 1 read Readable 8 W Writable MCKFS0 ...
Page 88
... GP_DATA4 GP_DATA3 GP_DATA2 GP_DATA1 R/W R/W R/W R 15:8 GP_PULL GPIO pullup resistor [7:0] 1: Enabled 0: Disabled CS5376A 16 DF Address: 0x0E GP_DIR0 R/W -- Not defined; 0 read Readable W Writable 8 R/W Readable and GP_PULL0 Writable R/W 1 Bits in bottom rows are reset condition (LSB) 0 GP_DATA0 R/W ...
Page 89
... GP_DATA11 GP_DATA10 GP_DATA9 R/W R/W R/W R 15:12 -- reserved 7:4 11:8 GP_PULL GPIO pullup resistor 3:0 [11:8] 1: Enabled 0: Disabled CS5376A 16 DF Address: 0x0F GP_DIR8 R/W -- Not defined; 0 read Readable 8 W Writable GP_PULL8 R/W Readable and R/W Writable 1 Bits in bottom rows are reset condition ...
Page 90
... Valid on rising edge, transition on falling edge 9 TM SPI2 timeout flag 1: SPI2 timed out 0: not timed out 8 D2SREQ Digital filter to SPI2 serial transaction request 1: Request operation 0: Operation complete (cleared by hardware) CS5376A 16 DF Address: 0x10 SPI2EN0 R/W -- Not defined; 1 read Readable 8 W Writable ...
Page 91
... R/W R/W R SCMD4 SCMD3 SCMD2 SCMD1 R/W R/W R/W R 15:8 SCMD[15:8] SPI2 Upper Command Byte CS5376A 16 DF Address: 0x11 -- -- Not defined; R/W read Readable W Writable 8 R/W Readable and SCMD8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 SCMD0 R/W 0 15:8 ...
Page 92
... R/W R/W R SDAT4 SDAT3 SDAT2 SDAT1 R/W R/W R/W R 15:8 SDAT[15:8] SPI2 Middle Data Byte CS5376A 16 DF Address: 0x12 SDAT16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and SDAT8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 SDAT0 R/W 0 ...
Page 93
... FSEL[2:0] Output filter stage select 111: reserved 110: reserved 101: IIR 3rd Order 100: IIR 2nd Order 011: IIR 1st Order 010: FIR2 Output 001: FIR1 Output 000: SINC Output CS5376A 16 DF Address: 0x20 EXP0 -- Not defined; R/W read Readable ...
Page 94
... R/W R/W R GAIN4 GAIN3 GAIN2 GAIN1 R/W R/W R/W R 15:8 GAIN[15:8] Gain Correction Middle Byte CS5376A 16 DF Address: 0x21 GAIN16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and GAIN8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 GAIN0 R/W 0 ...
Page 95
... R/W R OFST4 OFST3 OFST2 OFST1 R/W R/W R/W R 15:8 OFST[15:8] Offset Correction Middle Byte CS5376A 16 DF Address: 0x25 OFST16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and OFST8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 OFST0 R/W 0 15:8 ...
Page 96
... R/W R TBRK4 TBRK3 TBRK2 TBRK1 R/W R/W R/W R 15:8 TBRK[15:8] Time Break Counter Middle Byte CS5376A 16 DF Address: 0x29 TBRK16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and TBRK8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 TBRK0 R/W ...
Page 97
... No sync 10:8 CDLY[2:0] TBSCLK output phase delay 111: 7/8 period 110: 3/4 period 101: 5/8 period 100: 1/2 period 011: 3/8 period 010: 1/4 period 001: 1/8 period 000: none CS5376A 16 DF Address: 0x2A INTP0 -- Not defined; R/W read Readable W Writable ...
Page 98
... R TGAIN4 TGAIN3 TGAIN2 TGAIN1 R/W R/W R/W R 15:8 TGAIN[15:8] Test Bit Stream Gain Middle Byte CS5376A 16 DF Address: 0x2B TGAIN16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and TGAIN8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 TGAIN0 R/W ...
Page 99
... R SYS4 SYS3 SYS2 SYS1 R/W R/W R/W R 15:8 SYS[15:8] System Register 15:8 Middle Byte CS5376A 16 DF Address: 0x2C SYS16 -- Not defined; R/W read Readable W Writable 8 R/W Readable and SYS8 Writable R/W 0 Bits in bottom rows are reset condition (LSB) 0 SYS0 R/W 0 SYS[7:0] ...
Page 100
... ROM4 ROM3 ROM2 ROM1 R/W R/W R/W R 15:8 HW Hardware Revision 7:4 [7: CS5376 Rev CS5376 Rev CS5376A Rev A CS5376A 16 DF Address: 0x2E TYPE0 -- Not defined; R/W read Readable W Writable 8 R/W Readable and HW0 Writable R/W 1 Bits in bottom rows are reset condition (LSB) 0 ...
Page 101
... R/W R 15:12 DRAM Data RAM Test [3:0] ‘A’: Pass ‘F’: Fail 11:8 PRAM Program RAM Test [3:0] ‘A’: Pass ‘F’: Fail CS5376A 16 DF Address: 0x2F EU0 -- Not defined; R/W read Readable W Writable 8 R/W Readable and PRAM0 Writable ...
Page 102
... VDD2 12 13 MCLK/2 14 MCLK 15 MSYNC 2425 26 2728 29 30 3132 MDATA4 MFLAG4 MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 GND GND2 DS612F4 CS5376A BOOT RESET VDD1 GND1 SINT MOSI MISO SSI SCK1 SSO GPIO11:EECS 47 GPIO10 46 GPIO9 45 44 GPIO8 43 GPIO7 42 41 GPIO6 GND 38 37 ...
Page 103
... SPI 1 data, master out / slave in. Output SPI 1 serial interrupt output, active low. Reset Control Input Input Time Break Input CS5376A Pin Description JTAG reset, active low. JTAG test mode select. JTAG clock input. JTAG data input. JTAG data output. Do not connect. ...
Page 104
... SD port clock input. Output SD port token output. Input SD port token input. Power Supplies Supply Pin power supply for pins and 41 - 64. Supply Pin power supplies for pins 8 - 37. Supply Logic core power supplies. Supply CS5376A Pin Description Sync input. Digital grounds. DS612F4 ...
Page 105
... Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 CS5376A A A1 MILLIMETERS MIN MAX --- 1.60 0.15 0.27 12.30 10.10 12.30 10.10 0.60 0.75 7.00° ...
Page 106
... INFORMATION Model CS5376A-IQ CS5376A-IQZ Lead Free 27.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5376A-IQ CS5376A-IQZ Lead Free * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 28.REVISION HISTORY Revision Date PP1 SEP 2003 Initial “Preliminary Product” release. F1 FEB 2004 Update group delay, power consumption and MISO read timing. Add TBS impulse data and MISO pull-up ...