CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 25

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CS5368-DQZR

Manufacturer Part Number
CS5368-DQZR
Description
IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
Manufacturer
Cirrus Logic Inc
Datasheets

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Part Number:
CS5368-DQZR
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DS624A1
4.6.9 Master and Slave Clock Frequencies
MCLK Divider
MCLK (MHz)
SCLK(MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK(MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
LJ/I²S MASTER OR SLAVE
LJ/I²S MASTER OR SLAVE
LJ/I²S MASTER OR SLAVE
TDM MASTER OR SLAVE
Control Port Mode only
Tables 4 through 9
Mode, the device outputs the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set ac-
cording to design preference. However, device performance is guaranteed only when using the ratios
shown in the tables
.
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
Table 7. Frequencies for 48 kHz Sample Rate using TDM
show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. In Master
49.152
49.152
49.152
12.288
49.152
12.288
3.072
6.144
1024
1024
512
256
256
÷4
64
÷4
64
÷4
64
÷4
36.864
36.864
36.864
12.288
36.864
12.288
3.072
6.144
768
256
768
384
192
÷ 3
64
÷ 3
64
÷ 3
64
÷ 3
24.567
12.288
24.576
24.567
12.288
3.072
6.144
SSM
DSM
QSM
SSM
512
256
512
256
128
÷ 2
÷ 2
64
÷ 2
64
÷ 2
24
64
18.384
12.288
18.384
18.384
18.384
12.288
3.072
6.144
÷ 1.5
÷ 1.5
÷ 1.5
÷ 1.5
384
256
384
192
64
64
96
64
CS5368
12.288
12.288
12.288
12.288
12.288
12.288
3.072
6.144
256
256
256
128
÷ 1
÷ 1
64
÷ 1
64
÷ 1
64
64
29

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