CS43L42-KZ Cirrus Logic Inc, CS43L42-KZ Datasheet - Page 3

• Manufacturer Part Number: CS43L42-KZ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L42-KZ

• No. Of Pins: 24
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LIST OF FIGURES
DS481PP2
Figure 1. External Serial Mode Input Timing ............................................................ 11
Figure 2. Internal Serial Mode Input Timing ............................................................. 11
Figure 3. Internal Serial Clock Generation ............................................................... 11
Figure 4. Control Port Timing - Two-Wire Mode ....................................................... 12
Figure 5. Control Port Timing - SPI Mode ................................................................ 13
Figure 6. Typical Connection Diagram ..................................................................... 14
Figure 7. Control Port Timing, SPI mode .................................................................. 31
Figure 8. Control Port Timing, Two-Wire Mode ........................................................ 31
Figure 9. Base-Rate Stopband Rejection ................................................................. 32
Figure 10. Base-Rate Transition Band ..................................................................... 32
Figure 11. Base-Rate Transition Band (Detail) ......................................................... 32
Figure 12. Base-Rate Passband Ripple ................................................................... 32
Figure 13. High-Rate Stopband Rejection ................................................................ 32
Figure 14. High-Rate Transition Band ...................................................................... 32
Figure 15. High-Rate Transition Band (Detail) ......................................................... 33
Figure 16. High-Rate Passband Ripple .................................................................... 33
Figure 17. Line Output Test Load ............................................................................. 33
Figure 18. Headphone Output Test Load ................................................................. 33
Figure 19. CS43L42 Control Port Mode - Serial Audio Format 0 ............................. 34
Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1 ............................. 34
Figure 21. CS43L42 Control Port Mode - Serial Audio Format 2 ............................. 34
Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3 ............................. 35
Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 ............................. 35
Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 ............................. 35
Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6 ............................. 36
Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 ............................. 36
5. PIN DESCRIPTION ....................................................................................... 26
6. APPLICATIONS ........................................................................................... 29
7. CONTROL PORT INTERFACE .................................................................... 30
8. PARAMETER DEFINITIONS ........................................................................ 39
9. REFERENCES .............................................................................................. 39
10. PACKAGE DIMENSIONS ......................................................................... 40
4.10 Volume and Mixing Control (address 0Ah)....................................... 22
4.10.1 Tone Control MODE (TC)............................................................... 22
4.10.2 Tone Control Enable (TC_EN) ....................................................... 22
4.10.3 Peak Signal Limiter Enable (LIM_EN) ............................................ 23
4.10.4 ATAPI Channel Mixing and Muting (atapi) ..................................... 23
4.11 Mode Control 2 (address 0Bh) ......................................................... 24
4.11.1 Master Clock DIVIDE ENABLE (mclkdiv) ....................................... 24
4.11.2 Line Amplifier Gain Compensation (line) ........................................ 24
4.11.3 Digital Interface Format (dif) ........................................................... 24
6.1 Grounding and Power Supply Decoupling ........................................ 29
6.2 Clock Modes ...................................................................................... 29
6.3 De-Emphasis ..................................................................................... 29
6.4 Recommended Power-up Sequence ................................................ 29
6.5 PopGuard® Transient Control ........................................................... 29
7.1 SPI Mode ........................................................................................... 30
7.2 Two-Wire Mode ................................................................................. 30
7.3 Memory Address Pointer (MAP)
7.3.1 INCR (Auto Map Increment Enable)................................................. 31
7.3.2 MAP0-3 (Memory Address Pointer) ................................................. 31
............................................... 31
CS43L42
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