CS4384-CQZR Cirrus Logic Inc, CS4384-CQZR Datasheet - Page 27

• Manufacturer Part Number: CS4384-CQZR
• Description: IC - 192kHz 6and8 Channel D/A Conv
• Manufacturer: Cirrus Logic Inc

Specifications of CS4384-CQZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1525 - BOARD EVAL FOR CS4384 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS620F1
4.9
4.9.1
4.10
(64Fs)
BCKA
DSD Normal Mode
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4384 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the rec-
ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4384 should be connect-
ed to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
Analog Output and Filtering
The CS4384 does not include phase or amplitude compensation for an external filter. Therefore, the DAC
system phase and amplitude response will be dependent on the external analog circuitry.
Figure 23
Figure 24
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Note:
The CDB4384 evaluation board demonstrates the optimum layout and power supply arrangements.
DSD_SCLK
Not Used
Not Used
DSDAx,
DSDBx
shows how the full-scale analog output level specification is derived.
shows how the recommended output filtering with location for optional mute circuit.
All decoupling capacitors should be referenced to analog ground.
D0
D0
Figure 22. DSD Phase Modulation Mode Diagram
D1
D1
D1
D2
D2
DSDAx,
DSD_SCLK
DSD_SCLK
DSDBx
Not Used
Modulation Mode
DSD Phase
CS4384
(64Fs)
BCKD
(128Fs)
BCKA
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