CS4265-DNZR Cirrus Logic Inc, CS4265-DNZR Datasheet - Page 40

• Manufacturer Part Number: CS4265-DNZR
• Description: IC,Soundcard Circuits,LLCC,32PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4265-DNZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1001 - BOARD EVAL FOR CS4265 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

40
6.9
6.9.1
6.9.2
6.10
Reserved
7
ADC Input Control - Address 09h
DAC Channel A Volume Control - Address 0Ah
See
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
Analog Input Selection
Function:
These bits are used to select the input source for the PGA and ADC. Please see
6.11 DAC Channel B Volume Control - Address
Table
PGASoft
Reserved
0
0
1
1
6
13.
Table 13. PGA Soft Cross or Zero Cross Mode Selection
Reserved
Select
PGAZeroCross
Table
0
1
5
13.
0
1
0
1
(Bit 0)
Table 14. Analog Input Selection
PGASoft
4
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
Microphone-Level Input
Table
PGA/ADC Input
Line-Level Input
PGAZero
0Bh.
13.
3
Reserved
Mode
2
Reserved
Table
1
14.
CS4265
Select
DS657F2
0