CS42435-CMZ Cirrus Logic Inc, CS42435-CMZ Datasheet - Page 28

• Manufacturer Part Number: CS42435-CMZ
• Description: IC,Soundcard Circuits,CMOS,QFP,52PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

28
5.3
5.3.1
5.3.2
Analog Outputs
5.2.2.1
The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode. Software Mode.
The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high-pass filters are controlled us-
ing the HPF_FREEZE bit in the register
corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS42435 with the high-pass filter enabled until the filter settles. See the Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
Initialization
The initialization and Power-Down sequence flow chart is shown in
enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma
modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog
and analog-to-digital converters and switched-capacitor low-pass filters are powered down.
The device remains in the power-down state until the RST pin is brought high. The control port is acces-
sible once RST is high, and the desired register settings can be loaded per the interface descriptions in
the
pins must be set up before RST is brought high. All features will default to the Hardware Mode defaults
as listed in
VQ will quickly charge to VA/2 upon initial power up. Once MCLK is valid and the PDN bit is set to ‘0’b,
the internal voltage reference, FILT+, will ramp up to approximately VA. Power is applied to the D/A con-
verters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ.
Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK
frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
Line-Level Outputs and Filtering
The CS42435 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin-
gle-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approxi-
mately VQ.
The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low-pass filter.
See
for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a
passive filter configuration which minimizes costs and the number of components.
Figure 11
VA/2.
“Control Port Description and Timing” on page
Characteristics for filter settling time.
“DAC Output Filter” on page 50
shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately
Table
Hardware Mode
2.
for recommended output filter. The active filter configuration accounts
“ADC Control & DAC De-Emphasis (Address 05h)” on page
33. In Hardware Mode operation, the Hardware Mode
Figure 10 on page
29. The CS42438
CS42435
DS685F2
42.