CS2300P-DZZR Cirrus Logic Inc, CS2300P-DZZR Datasheet - Page 13

• Manufacturer Part Number: CS2300P-DZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS844PP2
5.4
5.4.1
Output to Input Frequency Ratio Configuration
SDATA
signal in order to maintain phase alignment. For these applications, it is advised to experiment with the
loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing
errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those syn-
chronous to the PLL_OUT domain.
While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is
achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-
rameter.
User Defined Ratio (R
The User Defined Ratio, R
desired input to output clock ratio. Up to four different ratios, Ratio
time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select
pins. The 32-bit R
format selectable by the LFRatioCfg global parameter.
The R
tion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication
factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See
User Defined Ratio” on page 24
The R
portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the
maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommend-
ed that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since
the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference
clock and the resolution of the R
MCLK
LRCK
SCLK
Referenced Control
ClkIn_BW[2:0]
Referenced Control
Ratio
LFRatioCfg
M[1:0]
0-3................................“Ratio 0 - 3” on page 21
....................................“M1 and M0 Mode Pin Functionality” on page 17
Wander < 128 Hz
UD
UD
for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por-
for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary
............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 22
.......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 23
D0
Figure 9. High bandwidth with CLK_IN domain re-use
UD
can be expressed in either a high resolution (12.20) or high multiplication (20.12)
Jitter
Parameter Definition
Parameter Definition
UD
UD
D1
CLK_IN
, is a 32-bit un-signed fixed-point number which determines the basis for the
)
UD
for more information.
or
.
Confidential Draft
BW = 128 Hz
PLL
Subclocks and data re-used
from previous clock domain.
3/18/09
PLL_OUT
0-3
, can be stored in the CS2300’s one
Wander < 128 Hz Passed to Output
SDATA
MCLK
LRCK
SCLK
Jitter > 128 Hz Rejected
CS2300-OTP
D0
“Calculating the
D1
13