CS2300CP-DZZR Cirrus Logic Inc, CS2300CP-DZZR Datasheet - Page 29

• Manufacturer Part Number: CS2300CP-DZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1406-2; CS2300CP-DZZR

DS843F1
9. CALCULATING THE USER DEFINED RATIO
Note:
Most calculators do not interpret the fixed point binary representation which the CS2300 uses to define the output
to input clock ratio (see
generate a binary or hex value which can be written to the Ratio register.
9.1
9.2
The software for use with the evaluation kit has built in tools to aid in calculating and converting the User
Defined Ratio. This section is for those who are not interested in the software or who are developing their
systems without the aid of the evaluation kit.
High Resolution 12.20 Format
To calculate the User Defined Ratio (R
cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in
High Multiplication 20.12 Format
To calculate the User Defined Ratio (R
cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in
Desired Output to Input Clock Ratio
Desired Output to Input Clock Ratio
11.2896 MHz/59.97 Hz =188254.127...
(output clock/input clock)
(output clock/input clock)
12.288 MHz/10 MHz=1.2288
12.288 MHz/60 Hz=204,800
11.2896 MHz/44.1 kHz=256
Section 5.3.1 on page
Table 2. Example 12.20 R-Values
Table 3. Example 20.12 R-Values
UD
UD
16); However, with a simple conversion we can use these tools to
) to store in the register(s), divide the desired output clock frequen-
) to store in the register(s), divide the desired output clock frequen-
(output clock/input clock)
(output clock/input clock)
Representation =
Representation =
Scaled Decimal
Scaled Decimal
268435456
838860800
771088904
1288490
Table
Table
2.
3.
•
•
2
2
20
12
Hex Representation of
Hex Representation of
00 13 A9 2A
2D F5 E2 08
Binary R
10 00 00 00
Binary R
32 00 00 00
CS2300-CP
20
12
UD
UD
to get the
to get the
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