CS2300CP-DZZ Cirrus Logic Inc, CS2300CP-DZZ Datasheet - Page 14

• Manufacturer Part Number: CS2300CP-DZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-DZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2
634 ms) after CLK_IN is removed (see
an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a
change in frequency causing clock skipping and the 2
to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2
the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See
put” on page
time listed in the
output will resume.
If it is expected that CLK_IN will be removed and then reapplied within 2
the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
note that the lower figure shows that the PLL output frequency may change and be incorrect without an
indication of an unlock condition.
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
CLK_IN
CLK_IN
“AC Electrical Characteristics” on page 7
Figure 11. CLK_IN removed for < 2
Figure 10. CLK_IN removed for > 2
ClkSkipEn= 1
ClkOutUnl=1
t
CS
2
23
LCO cycles
Lock Time
PLL_OUT
UNLOCK
2
CLK_IN
Figure
23
Lock Time
LCO cycles
10). This is true as long as CLK_IN does not glitch or have
t
CS
23
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
ClkSkipEn=0 or 1
ClkOutUnl=1
LCO cycle time-out to be bypassed and the PLL
23
Lock Time
after which lock will be acquired and the PLL
LCO cycles but > t
2
23
23
LCO cycles
PLL_OUT
LCO cycles
UNLOCK
PLL_OUT
UNLOCK
CLK_IN
CLK_IN
23
LCO cycles but later than t
23
CS
LCO cycles (518 ms to
= invalid clocks
t
CS
= invalid clocks
23
2
23
LCO cycles pass,
LCO cycles
CS2300-CP
Lock Time
“PLL Clock Out-
2
23
Lock Time
Figure
LCO cycles
DS843F1
CS
11;
,