CS2300CP-CZZR Cirrus Logic Inc, CS2300CP-CZZR Datasheet - Page 19

• Manufacturer Part Number: CS2300CP-CZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-CZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1405-2; CS2300CP-CZZR

DS843F1
5.4
5.5
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in
clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
Referenced Control
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 28
ClkOutDis
Referenced Control
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 25
AuxOutDis
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 27
PLL Output
0
..............................“PLL Clock Output Disable (ClkOutDis)” on page 25
.............................“Auxiliary Output Disable (AuxOutDis)” on page 24
Frequency Reference Clock
PLL Lock/Unlock Indication
2:1 Mux
0
1
ClkOutUnl
PLL Clock Output
Register Location
Register Location
(PLLClkOut)
Figure 16. PLL Clock Output Options
(CLK_IN)
Figure 17. Auxiliary Output Selection
(Lock)
PLL Locked/Unlocked
2:1 Mux
0
1
AuxOutSrc[1:0]
3:1 Mux
PLL Clock Output
PLLClkOut
section 8.6.2 on page
AuxOutDis
AuxLockCfg
ClkOutDis
Figure
17, to one of three signals: input
Auxiliary Output Pin
(AUX_OUT)
27). If AUX_OUT is set to
PLL Clock Output Pin
(CLK_OUT)
CS2300-CP
19