AM29LV033C-70EI AMD (ADVANCED MICRO DEVICES), AM29LV033C-70EI Datasheet - Page 4

• Manufacturer Part Number: AM29LV033C-70EI
• Description: IC 32MEG (4M X 8-BIT) 3V SCTR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Common Flash Memory Interface (CFI) . . . . . . . 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 24
Standard Products .................................................. 8
Requirements for Reading Array Data ................... 9
Writing Commands/Command Sequences ............ 9
Accelerated Program Operation ........................... 10
Program and Erase Operation Status .................. 10
Standby Mode ...................................................... 10
Automatic Sleep Mode ......................................... 10
RESET#: Hardware Reset Pin ............................. 10
Output Disable Mode ............................................ 11
Autoselect Mode ................................................... 13
Sector/Sector Block Protection and Unprotection 13
Temporary Sector/Sector Block Unprotect ........... 14
Hardware Data Protection .................................... 16
Low V
Write Pulse “Glitch” Protection ............................. 16
Logical Inhibit ....................................................... 16
Power-Up Write Inhibit ......................................... 16
Reading Array Data .............................................. 19
Reset Command .................................................. 19
Autoselect Command Sequence .......................... 19
Byte Program Command Sequence ..................... 19
Unlock Bypass Command Sequence ................... 20
Accelerated Program Operations ......................... 20
Chip Erase Command Sequence ......................... 20
Sector Erase Command Sequence ...................... 21
Erase Suspend/Erase Resume Commands ......... 21
DQ7: Data# Polling ............................................... 24
Table 1. Am29LV033C Device Bus Operations ............9
Table 2. Am29LV033C Sector Address Table ............11
Table 3. Am29LV033C Autoselect Codes
(High Voltage Method) ................................................13
Table 4. Sector Block Addresses for
Protection/Unprotection ...............................................14
Figure 1. Temporary Sector Unprotect Operation....... 14
Figure 2. In-System Sector Protect/
Unprotect Algorithms................................................... 15
Table 5. CFI Query Identification String ......................16
Table 6. System Interface String .................................17
Table 7. Device Geometry Definition ..........................17
Table 8. Primary Vendor-Specific Extended Query ....18
Figure 3. Program Operation ...................................... 20
Figure 4. Erase Operation........................................... 22
Table 9. Am29LV033C Command Definitions ...........23
CC
Write Inhibit ............................................ 16
Am29LV033C
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 28
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Key to Switching Waveforms . . . . . . . . . . . . . . . 31
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Erase and Programming Performance . . . . . . . 42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 42
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 42
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
RY/BY#: Ready/Busy# ......................................... 25
DQ6: Toggle Bit I .................................................. 25
DQ2: Toggle Bit II ................................................. 25
Reading Toggle Bits DQ6/DQ2 ............................ 25
DQ5: Exceeded Timing Limits .............................. 26
DQ3: Sector Erase Timer ..................................... 26
CMOS Compatible ............................................... 29
Zero Power Flash ................................................. 30
Read Operations .................................................. 32
Hardware Reset (RESET#) .................................. 33
Erase/Program Operations ................................... 34
TS 040—40-Pin Standard TSOP ......................... 43
TSR040—40-Pin Reverse TSOP ........................ 44
FBD063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 14 mm ............................................... 45
Revision B (January 3, 2000) ............................... 46
Revision B+1 (February 21, 2000) ....................... 46
Revision B+2 (November 7, 2000) ....................... 46
Figure 5. Data# Polling Algorithm................................ 24
Figure 6. Toggle Bit Algorithm..................................... 26
Table 10. Write Operation Status ................................27
Figure 9. I
and Automatic Sleep Currents) ................................... 30
Figure 10. Typical I
Figure 11. Test Setup.................................................. 31
Table 11. Test Specifications ......................................31
Figure 12. Input Waveforms and
Measurement Levels ................................................... 31
Figure 13. Read Operations Timings .......................... 32
Figure 14. RESET# Timings........................................ 33
Figure 15. Program Operation Timings ....................... 35
Figure 16. Accelerated Program Timing Diagram ....... 35
Figure 17. Chip/Sector Erase Operation Timings........ 36
Figure 18. Data# Polling Timings (During
Embedded Algorithms)................................................ 37
Figure 19. Toggle Bit Timings (During
Embedded Algorithms)................................................ 37
Figure 20. DQ2 vs. DQ6.............................................. 37
Figure 21. Temporary Sector/Sector
Block Unprotect Timing Diagram................................. 38
Figure 22. Sector Protect/Unprotect
Timing Diagram ........................................................... 39
Figure 23. Alternate CE# Controlled Write
Operation Timings ....................................................... 41
CC1
Current vs. Time (Showing Active
CC1
vs. Frequency ......................... 30
3