AM29LV033C-70EI AMD (ADVANCED MICRO DEVICES), AM29LV033C-70EI Datasheet - Page 17

• Manufacturer Part Number: AM29LV033C-70EI
• Description: IC 32MEG (4M X 8-BIT) 3V SCTR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
and power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until V
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
16
Addresses
CC
CC
1Ah
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
CC
Write Inhibit
is greater than V
is less than V
LKO
Data
51h
52h
59h
02h
00h
40h
00h
00h
00h
00h
00h
LKO
, the device does not ac-
. The system must pro-
Table 5. CFI Query Identification String
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
CC
power-up
Am29LV033C
CC
vide the proper signals to the control pins to prevent
unintentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
given in Tables 5–8. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
IL
, CE# = V
Description
IH
or WE# = V
IL
and OE# = V
IH
CC
. To initiate a write cycle,
is greater than V
IH
during power up,
LKO
.