AM29F400BB-70SD Spansion Inc., AM29F400BB-70SD Datasheet
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AM29F400BB-70SD
Specifications of AM29F400BB-70SD
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AM29F400BB-70SD Summary of contents
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Am29F400B Data Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made ...
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DATA SHEET Am29F400B 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 5.0 volt-only operation for read, erase, and program operations — Minimizes system level ...
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GENERAL DESCRIPTION The Am29F400B Mbit, 5.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) ...
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... Program and Erase Operation Status ...................................... 9 Standby Mode .......................................................................... 9 RESET#: Hardware Reset Pin ................................................. 9 Output Disable Mode ................................................................ 9 Table 2. Am29F400BT Top Boot Block Sector Address Table ....... 10 Table 3. Am29F400BB Bottom Boot Block Sector Address Table.. 10 Autoselect Mode ..................................................................... 10 Table 4. Am29F400B Autoselect Codes (High Voltage Method) .... 11 Sector Protection/Unprotection ............................................... 11 Temporary Sector Unprotect .................................................. 11 Figure 1 ...
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PRODUCT SELECTOR GUIDE Family Part Number V = 5.0 V ± Speed Option V = 5.0 V ± 10% CC Max access time ACC Max CE# access time Max OE# access ...
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CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21258 for more information. A15 1 A14 2 A13 3 A12 4 5 A11 A10 ...
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PIN CONFIGURATION A0–A17 = 18 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# ...
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... SC, SD, SI, SF, SE, SK AM29F400BT-55, AM29F400BB-55 EC0, ED0, EI0, AM29F400BT-55, EF0, EE0, EK0, AM29F400BB-55 SC0, SD0, SI0, SF0, SE0, SK0 AM29F400BT-70, AM29F400BB-70 EC, ED, EI, AM29F400BT-90, EF, EE, EK AM29F400BB-90 SC, SD, SI, SF, SE, SK AM29F400BT-120, AM29F400BB-120 November 1, 2006 21505E5 OPTIONAL PROCESSING Blank = Standard Processing 5.0 V ± 10 device only ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is composed of ...
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After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in ...
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... Table 2. Am29F400BT Top Boot Block Sector Address Table Sector A17 A16 A15 A14 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Table 3. Am29F400BB Bottom Boot Block Sector Address Table Sector A17 A16 A15 A14 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Note: Address range is A17:A-1 in byte mode and A17:A0 in word mode.See the “ ...
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Table 4. Am29F400B Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: AMD L Device ID: Word L Am29F400B Byte L (Top Boot Block) Device ID: Word L Am29F400B Byte L (Bottom Boot Block) Sector Protection Verification L L ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadver tent writes (refer to Table 5 for command definitions). In addition, the following hard- ware data protection measures prevent accidental erasure ...
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COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the ...
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The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “The Erase Resume command is valid only during the Erase Suspend mode.” for information on these status bits. ...
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It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the ...
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Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector ...
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Table 5. Am29F400B Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsec- tions describe the functions of these bits. DQ7, RY/ BY#, and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as ...
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Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS TTL/NMOS Compatible Parameter Description I Input Load Current LI A9, OE#, RESET# Input Load I LIT Current I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I ...
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DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current LI A9, OE#, RESET# I LIT Input Load Current I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I ...
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TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent. Figure 8. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted November 1, 2006 21505E5 ...
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AC CHARACTERISTICS Read Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std Description t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY# t VCS V CC Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE# OE# WE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use either CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes Program Address Program Data Sector Address, DQ7# = Complement ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 programming typicals ...
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PHYSICAL DIMENSIONS TS 048—48-Pin Standard Thin Small Outline Package November 1, 2006 21505E5 Am29F400B Dwg rev AA; 10/99 37 ...
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PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package Am29F400B Dwg rev AC; 10/99 21505E5 November 1, 2006 ...
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REVISION SUMMARY Revision A (August 1997) Initial release. Revision B (October 1997) Global Added -55 and -60 speed options, deleted -65 speed option. Changed data sheet designation from Advance Information to Preliminary. Connection Diagrams Corrected pinouts on all packages: deleted ...
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General Description Third paragraph: Added access times. Product Selector Guide Added the -45 speed option for V CC the -55 speed option for V = 5.0 V ± 10%. CC Ordering Information Added “Special Designation” to “Optional ...
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... Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...