ADV7393BCPZ-REEL Analog Devices Inc, ADV7393BCPZ-REEL Datasheet - Page 98

IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC

ADV7393BCPZ-REEL

Manufacturer Part Number
ADV7393BCPZ-REEL
Description
IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7393BCPZ-REEL

Design Resources
Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
Applications
Set-Top Boxes, Video Players, Displays
Voltage - Supply, Analog
2.6 V ~ 3.46 V
Voltage - Supply, Digital
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADV7390/ADV7391/ADV7392/ADV7393
Table 97. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x8C
0x8D
0x8E
0x8F
Setting
0x02
0x1C
0x10
0x00
0x11
0xD3
0x0C
0x8C
0x79
0x26
Description
Software reset.
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
Rev. B | Page 98 of 108
Table 98. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
0x8C
0x8D
0x8E
0x8F
0x02
0x1C
0x00
0x11
0xD3
0x80
0x10
0x0C
0x0C
0x8C
0x79
0x26
Setting
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).

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