ADV7393BCPZ-REEL Analog Devices Inc, ADV7393BCPZ-REEL Datasheet - Page 39

IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC

ADV7393BCPZ-REEL

Manufacturer Part Number
ADV7393BCPZ-REEL
Description
IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7393BCPZ-REEL

Design Resources
Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
Applications
Set-Top Boxes, Video Players, Displays
Voltage - Supply, Analog
2.6 V ~ 3.46 V
Voltage - Supply, Digital
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 29. Register 0x88 to Register 0x89
SR7 to
SR0
0x88
0x89
1
Table 30. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
Available on the ADV7392/ADV7393 (40-pin devices) only.
SD Mode Register 7
SD Mode Register 8
Register
Register
SD Timing Register 0
Bit Description
Reserved
SD noninterlaced mode
SD double buffering
SD input format
SD digital noise reduction
SD gamma correction enable
SD gamma correction curve select
SD undershoot limiter
Reserved
Reserved
SD chroma delay
Reserved
Bit Description
SD slave/master mode
SD timing mode
Reserved
SD luma delay
SD minimum luma value
SD timing reset
Rev. B | Page 39 of 108
7
x
7
0
1
0
6
0
1
6
0
1
0
5
0
1
0
0
1
1
5
0
0
1
1
Bit Number
ADV7390/ADV7391/ADV7392/ADV7393
Bit Number
4
0
0
1
1
0
1
0
1
4
0
1
0
1
3
0
1
0
1
0
3
1
2
0
1
0
1
2
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
Register Setting
Disabled.
Enabled.
Disabled.
Enabled.
8-bit YCbCr input.
16-bit YCbCr input.
10-bit YCbCr/16-bit SD RGB
input.
Reserved.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
0 must be written to this bit.
Reserved.
Disabled.
4 clock cycles.
8 clock cycles.
Reserved.
0 must be written to these bits.
0
0
1
1
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
No delay.
Two clock cycles.
Four clock cycles.
Six clock cycles.
−7.5 IRE.
A low-high-low transition
resets the internal SD
timing counters.
−40 IRE.
1
Reset
Value
0x00
0x00
Reset
Value
0x08

Related parts for ADV7393BCPZ-REEL