ADV7179KCP Analog Devices Inc, ADV7179KCP Datasheet - Page 32

• Manufacturer Part Number: ADV7179KCP
• Description: IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,CERAMIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7179KCP

• Rohs Status: RoHS non-compliant
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 2.8 V, 3.3 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Voltage - Supply, Digital: -

ADV7174/ADV7179
MODE REGISTER 4 (MR4)
Bits:
Address:
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
Table 14. MR4 Bit Description
Bit Name
Output Select
RGB/YPbPr Control
RGB Sync
VSYNC_3H
Pedestal Control
Active Video Filter Control
Sleep Mode Control
Reserved
MR47–MR40
SR4–SR0 = 04H
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR47
MR47
(0)
Bit No.
MR40
MR41
MR42
MR43
MR44
MR45
MR46
MR47
MR46
SLEEP MODE
0
1
CONTROL
MR46
DISABLE
ENABLE
MR45
FILTER CONTROL
0
1
ACTIVE VIDEO
DISABLE
ENABLE
MR45
Description
This bit specifies if the part is in composite video or RGB/YPbPr mode.
This bit enables the output from the RGB DACs to be set to YPbPr output video standard.
This bit is used to set up the RGB outputs with the sync information encoded on all RGB
outputs.
When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low
input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in
master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines
in NTSC mode and 2.5 lines in PAL mode.
This bit specifies whether a pedestal is to be generated on the NTSC composite video
signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode.
This bit controls the filter mode applied outside the active video portion of the line. This
filter ensures that the sync rise and fall times are always on spec regardless of which luma
filter is selected. A Logic 1 enables this mode.
When this bit is set (1), sleep mode is enabled. With this mode enabled, the
ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I
can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is
set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep
mode and resumes normal operation. Also, if the RESET signal is applied during sleep
mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation.
A Logic 0 should be written to this bit.
MR44
0
1
PEDESTAL
CONTROL
PEDESTAL OFF
PEDESTAL ON
MR44
Figure 42. Mode Register 4
Rev. B | Page 32 of 52
MR43
0
1
VSYNC_3H
MR43
DISABLE
ENABLE
MR42
0
1
RGB SYNC
MR42
DISABLE
ENABLE
MR41
0
1
CONTROL
RGB/YUV
MR41
RGB OUTPUT
YPbPr OUTPUT
MR40
0
1
OUTPUT SELECT
MR40
YC OUTPUT
RGB/YPbPr OUTPUT
2
C registers