ADV7171KSUZ-REEL Analog Devices Inc, ADV7171KSUZ-REEL Datasheet - Page 19

• Manufacturer Part Number: ADV7171KSUZ-REEL
• Description: IC,TV/VIDEO CIRCUIT,Color Encoder Circuit,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7171KSUZ-REEL

• Applications: Set-Top Boxes, Video Players
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/post-
equalization pulses (see Figure 21 to Figure 32). This mode of
operation is called “partial blanking” and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YcbCr data stream (for example, WSS data,
CGMS, VPS, and so on). Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
RTC
NOTES:
1
2
3
F
F
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET BIT
RESET ADV7170/ADV7171 DDS
SC
SC
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7170/ADV7171 FSC DDS REGISTER IS
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
NTSC/PAL M SYSTEM
(625 LINES/50Hz)
(525 LINES/60Hz)
H/LTRANSITION
COUNT START
INPUT PIXELS
PAL SYSTEM
TIME SLOT: 01
COMPOSITE VIDEO
128
ANALOG
VCR OR CABLE)
(FOR EXAMPLE,
VIDEO
LOW
13
ADV7170/ADV7171
NOT USED IN
Y
END OF ACTIVE
RESERVED
14 BITS
VIDEO LINE
C
r
Y
(FOR EXAMPLE,
F
F
4 CLOCK
EAV CODE
4 CLOCK
DECODER
ADV7185)
0
0
VIDEO
0
0
0
14
RESERVED
X
Y
Figure 19. RTC Timing and Connections
Figure 20. Timing Mode 0 (Slave Mode)
4 BITS
8
0
19
1
0
21
8
0
Rev. C | Page 19 of 64
1
0
ANCILLARY DATA
0
0
268 CLOCK
280 CLOCK
CLOCK
SCRESET/RTC
P7–P0
HSYNC
FIELD/VSYNC
F
F
(HANC)
ADV7170/ADV7171
F
F
SAMPLE
A
B
F
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 are controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchroni-
zation pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
Mode 0 is shown in Figure 20. The HSYNC, FIELD/VSYNC,
and BLANK (if not used) pins should be tied high during this
mode.
VALID
SC
A
B
BLUE/COMPOSITE/U
PLL INCREMENT
A
B
RED/CHROMA/V
GREEN/LUMA/Y
SAMPLE
INVALID
COMPOSITE
8
0
1
0
8
0
1
1
0
SAV CODE
4 CLOCK
F
F
4 CLOCK
START OF ACTIVE
0
0
VIDEO LINE
0
0
X
Y
C
b
RESERVED
Y C
8/LLC
1440 CLOCK
1440 CLOCK
5 BITS
r
Y
0
SEQUENCE
C
b
ADV7170/ADV7171
BIT
Y
C
r
2
67 68
Y
RESET
C
b
BIT
3
RESERVED