ADV7171 Analog Devices, ADV7171 Datasheet

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... DAC C (PIN 26) DAC 10-BIT DAC B (PIN 31) E DAC 10-BIT DAC A (PIN 32) 10 DAC V ADV7170/ADV7171 SIN/COS VOLTAGE DDS BLOCK REFERENCE R CIRCUIT COMP GND World Wide Web Site: http://www.analog.com © Analog Devices, Inc., 1998 2 C) REF SET ...

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... ADV7170/ADV7171–SPECIFICATIONS 5 V SPECIFICATIONS ( Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage ...

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... SET OUT R = 150 , R = 37.5 SET 1041 , R = 262.5 SET L COMP = 0 150 and R = 37.5 ), optimum performance obtained DAC current ( 110 C. J –3– ADV7170/ADV7171 2 . All specifications unless otherwise noted.) MIN MAX Min Typ Max 2 ...

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... ADV7170/ADV7171–SPECIFICATIONS 5 V DYNAMIC SPECIFICATIONS Parameter 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 SNR (Pedestal SNR (Pedestal SNR (Ramp SNR (Ramp Hue Accuracy 3, 4 Color Saturation Accuracy 3, 4 Chroma Nonlinear Gain ...

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... AA REF otherwise noted.) Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and –5– ADV7170/ADV7171 = 150 . All specifications SET MIN MAX Min Typ ...

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... ADV7170/ADV7171–SPECIFICATIONS 3.3 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time, t ...

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... Figure 1. MPU Port Timing Diagram Figure 2. Pixel and Control Data Timing Diagram 4 CLOCK 4 CLOCK CYCLES CYCLES Figure 3. Teletext Timing Diagram –7– ADV7170/ADV7171 CLOCK 4 CLOCK CYCLES CYCLES ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7170/ADV7171 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... MPU Port Serial Data Input/Output. TTL Address Input. This signal set up the LSB of the MPU address. The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 Composite and S Video out and DAC B powered ON and DAC D powered OFF ...

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... Y typically has a range 235, Cr and Cb typically have a range of 128 to input data from 1 to 254 on both Y, Cb and Cr. The ADV7170/ ADV7171 supports PAL ( and NTSC (with and without pedestal) standards. The appropriate SYNC, BLANK and Burst levels are added to the YCrCb data ...

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... FREQUENCY – MHz Figure 8. NTSC Notch Luma Filter REV Figure 10. Extended Mode (SSAF) Luma Filter –11– ADV7170/ADV7171 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 9. PAL Notch Luma Filter 0 – ...

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... ADV7170/ADV7171 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 12. QCIF Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 13. 1.3 MHz Low-Pass Chroma Filter 0 –10 –20 –30 –40 –50 –60 –70 ...

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... These are enabled by setting MR17 of Mode Register 1 to Logic “1.” SQUARE PIXEL MODE The ADV7170/ADV7171 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accord- ingly for square pixel mode operation ...

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... Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...

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... Register 0 TR0 = The ADV7170/ADV7171 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/VSYNC pin ...

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... ADV7170/ADV7171 DISPLAY 622 623 624 625 H V EVEN FIELD F DISPLAY 309 310 311 312 ODD FIELD ANALOG VIDEO Figure 23. Timing Mode 0 Data Transitions (Master Mode) VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 313 314 315 316 ...

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... Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis- abled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624 ...

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... Register 0 TR0 = this mode the ADV7170/ADV7171 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. ...

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... HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus- trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data ...

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... In this mode the ADV7170/ADV7171 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 31 (NTSC) and Figure 32 (PAL). ...

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... RESET pin. This initializes the pixel port so that the pixel inputs, P7–P0 are selected. After reset, the ADV7170/ ADV7171 is automatically set up to operate in NTSC mode. Subcarrier frequency code 21F07C16HEX is loaded into the subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. All bits in Mode Register 0 are set to Logic Level “ ...

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... MR0 BIT DESCRIPTION Encode Mode Control (MR01–MR00) These bits are used to set up the encode mode. The ADV7170/ ADV7171 can be set up to output NTSC, PAL ( and PAL (M, N) standard video. Luminance Filter Control (MR02–MR04) These bits specify which luma filter selected. The filter ...

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... SR7 SR6 SR5 SR4 SR7–SR5 (000) ZERO SHOULD BE WRITTEN TO THESE BITS ADV7171 SUBADDRESS REGISTER SR5 SR4 SR3 SR2 SR1 SR0 MODE REGISTER MODE REGISTER MODE REGISTER MODE REGISTER 3 ...

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... DAC Control (MR16–MR13) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7170/ ADV7171 if any of the DACs are not required in the application. MR17 DAC A CONTROL MR16 ...

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... Burst Control (MR25) This bit enables the burst information to be switched on and off the video output. Low Power Control (MR26) This bit enables the lower power mode of the ADV7170/ADV7171. This will reduce the DAC current by 45%. Reserved (MR27) A Logical 0 must be written to this bit. ...

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... When this bit is set (“1”) Sleep Mode is enabled. With this mode enabled, the ADV7170/ADV7171 power consumption is reduced to typically 200 nA. The I and read from when the ADV7170/ADV7171 is in Sleep Mode. If MR46 is set to a (“0”) when the device is in Sleep Mode, the ADV7170/ADV7171 will come out of Sleep Mode and resume normal operation ...

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... These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output. HSYNC to FIELD Delay Control (TR15–TR14) When the ADV7170/ADV7171 is in timing mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15–TR14) When the ADV7170/ADV7171 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth ...

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... ADV7170/ADV7171 SUBCARRIER FREQUENCY REGISTER 3–0 (FSC3–FSC0) (Address [SR4–SR0] = 09H–02H) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation –1 Subcarrier Frequency Register = F CLK i.e.: NTSC Mode MHz, CLK ...

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... When this bit is enabled (“1”), the last six bits of the CGMS data, i.e., the CRC check sequence, is calculated internally by the ADV7170/ADV7171. If this bit is disabled (“0”) the CRC values in the register are output to the CGMS data stream. CGMS Odd Field Control (C/W05) When this bit is set (“ ...

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... AA 0.1 F decoupling capacitor to GND. These capacitors should be placed as close to the device as possible important to note that while the ADV7170/ADV7171 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane ...

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... The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the correct sequence. CLOCK HSYNC REV ...

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... FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7170/ADV7171 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems ...

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... Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7170/ADV7171 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a refer- ence pulse of the same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers in the following order ...

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... The ADV7170/ADV7171 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7170/ADV7171 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 58). ...

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... ADV7170/ADV7171 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such PD that it appears t = 10.2 s after the leading edge of the horizontal signal. Time TXT SYNTXTOUT source that is gated by the TTREQ signal in order to deliver TTX data. ...

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... ADV7170/ADV7171 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 1067.7mV 286mV (pk-pk) 650mV 232.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 6 NTSC WAVEFORMS (WITH PEDESTAL) Figure 61. NTSC Composite Video Levels Figure 62. NTSC Luma Video Levels 835mV (pk-pk) Figure 63 ...

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... IRE REV. 0 NTSC WAVEFORMS (WITHOUT PEDESTAL) Figure 65. NTSC Composite Video Levels Figure 66. NTSC Luma Video Levels Figure 67. NTSC Chroma Video Levels Figure 68. NTSC RGB Video Levels –37– ADV7170/ADV7171 PEAK COMPOSITE 1289.8mV REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL 338mV SYNC LEVEL 52 ...

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... ADV7170/ADV7171 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 1092.5mV 300mV (pk-pk) 650mV 207.5mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS Figure 69. PAL Composite Video Levels Figure 70. PAL Luma Video Levels 885mV (pk-pk) Figure 71. PAL Chroma Video Levels Figure 72. PAL RGB Video Levels –38– ...

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... Figure 76. NTSC 100% Color Bars, No Pedestal V Levels 467mV BETACAM LEVEL 0mV Figure 77. NTSC 100% Color Bars with Pedestal V Levels 350mV SMPTE LEVEL 0mV Figure 78. PAL 100% Color Bars, V Levels –39– ADV7170/ADV7171 505mV 423mV 82mV 0mV –82mV –423mV –505mV 467mV 391mV ...

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... FREQUENCY – Hz Figure 80. Output Filter Plot APPENDIX 7 OPTIONAL OUTPUT FILTER is not required if the outputs of the ADV7170/ADV7171 are connected to most analog monitors or analog TVs, however if the output signals are applied to a system where sampling is used (e.g., Digital TVs), then a filter is required to prevent aliasing. ...

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... When external buffering is needed of the ADV7170/ADV7171 DAC outputs, the configuration in Figure 83 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7170/ADV7171 to dissipate less power; the analog cur- rent is reduced by 50% with 300 SET This mode is recommended for 3 ...

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... ADV7170/ADV7171 The ADV7170/ADV7171 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Addi- tionally, the burst and color information are enabled on the output and the internal color bar generator is switched off ...

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... CGMS_WSS Reg 2 19Hex TeleText Control Register REV. 0 Data 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Data 00Hex 58Hex 00Hex 00Hex 10Hex 00Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex –43– ADV7170/ADV7171 ...

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... ADV7170/ADV7171 0.6 0.4 0.2 0.0 0.2 0.0 10.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 0.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s APPENDIX 10 OUTPUT WAVEFORMS L608 20.0 30.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 85. 100%/75% PAL Color Bars L575 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF ...

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... SLOW CLAMP TO 0. 6.72 s REV. 0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS Figure 87. 100%/75% PAL Color Bars Chrominance 0.0 F1 L76 10.0 20.0 30.0 MICROSECONDS PRECISION MODE OFF NO FILTERING Figure 88. 100%/75% NTSC Color Bars –45– ADV7170/ADV7171 50.0 60.0 NO BRUCH SIGNAL SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 40.0 50.0 60.0 SYNCHRONOUS SYNC = A FRAMES SELECTED ...

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... ADV7170/ADV7171 0.6 0.4 50.0 0.2 0.0 0.0 –0.2 10.0 NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 0.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s Figure 90. 100%/75% NTSC Color Bars Chrominance F2 L238 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING Figure 89 ...

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... Figure 91. PAL Vector Plot R 100% 75 Figure 92. NTSC Vector Plot –47– ADV7170/ADV7171 SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V & – SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB ...

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... ADV7170/ADV7171 COLOR BAR (NTSC) FIELD = 2 LINE = 28 LUMINANCE LEVEL (IRE) 0.4 0.2 30.0 20.0 10.0 0.0 –10.0 CHROMINANCE LEVEL (IRE) 0.0 –0.2 1.0 0.0 –1.0 CHROMINANCE PHASE (DEG –0.1 0.0 –1.0 –2.0 GRAY AVERAGE: 32 --> 32 DGDP (NTSC) BLOCK MODE START F2 L64, STEP = 32, END = 192 DIFFERENTIAL GAIN (%) 0.00 0.3 0.2 0.1 0.0 –0.1 DIFFERENTIAL PHASE (DEG) 0.00 0.20 0.15 0.10 0.05 –0.00 –0.05 – ...

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... WITH AGC FOR 100% CHROMINANCE LEVEL) REV. 0 WFM --> pk-pk = 0.2 100.0 99.9 99.9 2ND 3RD 4TH WFM --> –68.4dB RMS –70.0 –65.0 –60.0 –55.0 –50.0 –64.4dB RMS –70.0 –65.0 –60.0 –55.0 –50.0 Figure 96. NTSC AMPM Noise Measurement –49– ADV7170/ADV7171 5 STEP 99.8 5TH APPROPRIATE –45.0 –40.0 dB RMS –45.0 –40.0 dB RMS ...

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... ADV7170/ADV7171 NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE ( 714mV p-p) BANDWIDTH 100kHz TO FULL –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE ( 714mV p-p) BANDWIDTH 10kHz TO FULL (TILT NULL) – ...

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... R –218.70 –42.54 41.32 –0.51% 0.69% –0.76% 1.40% R-Y 514.90mV –1.92% DELAY: B-Y –6ns R-Y –6ns Figure 100. PAL YUV Lighting Plot –51– ADV7170/ADV7171 mV Pr(C) 250 200 150 100 50 0 –50 –100 –150 –200 –250 AVERAGE 32 --> 174.35 260.51 –0.65% –0.14% CY 864.78 – ...

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... ADV7170/ADV7171 COMPONENT NOISE LINE = 202 AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 10kHz TO 5.0MHz 0.0 –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 COMPONENT MULTIBURST LINE = 202 AMPLITUDE (0dB = 100% OF 0.04 0.0 Y –5.0 –10.0 ...

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... COMPONENT VECTOR SMPTE/EBU, 75 Figure 103. PAL YUV Vector Plot mV BLUE (B) 700 600 500 400 300 200 100 0 100 200 300 Figure 104. PAL RGB Waveforms –53– ADV7170/ADV7171 RED (C) 700 600 500 400 300 200 100 0 100 200 300 ...

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... ADV7170/ADV7171 INDEX Contents FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1 ADV7170/ADV7171 SPECIFICATIONS . . . . . . . . . . . . . 2 DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 4 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 8 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 10 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 10 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 10 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 13 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 13 COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13 BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13 NTSC PEDESTAL CONTROL ...

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... Thin Plastic Quad Flatpack (TQFP) (SU-44) 0.047 (1.20) MAX 0.006 (0.15) 0.472 (12.00) SQ 0.002 (0.05 SEATING PLANE TOP VIEW (PINS DOWN 0.041 (1.05) 0.018 (0.45) 0.031 (0.80) BSC 0.037 (0.95) 0.012 (0.30) –55– ADV7170/ADV7171 0.016 (0.41) 0.012 (0.30 0.394 (10. ...