ADN2892ACPZ-RL Analog Devices Inc, ADN2892ACPZ-RL Datasheet

IC,Application Specific Amplifier,SINGLE,LLCC,16PIN,PLASTIC

ADN2892ACPZ-RL

Manufacturer Part Number
ADN2892ACPZ-RL
Description
IC,Application Specific Amplifier,SINGLE,LLCC,16PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADN2892ACPZ-RL

Amplifier Type
Limiting
Number Of Circuits
1
-3db Bandwidth
1.5GHz
Voltage - Input Offset
100µV
Current - Supply
48mA
Voltage - Supply, Single/dual (±)
2.9 V ~ 3.6 V
Operating Temperature
-40°C ~ 95°C
Mounting Type
Surface Mount
Package / Case
16-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
Current - Output / Channel
-
Slew Rate
-
Gain Bandwidth Product
-
Current - Input Bias
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Input sensitivity: 3.5 mV p-p
70 ps rise/fall times
CML outputs: 750 mV p-p differential
Bandwidth selectable for multirate 1×/2×/4× FC modules
Optional LOS output inversion
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
Single-supply operation: 3.3 V
Low power dissipation: 160 mW
Available in space-saving, 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
1×, 2×, and 4× FC transceivers
SFP/SFF/GBIC optical transceivers
GbE transceivers
Backplane receivers
Rev. 0.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SFF-8472-compliant average power measurement
ADN2882
PD_CATHODE
PD_VCC
PIN
NIN
Figure 1. RSSI Function Capable—Applications Setup Block Diagram
50Ω
ADN2892
AVCC
3.5kΩ
FUNCTIONAL BLOCK DIAGRAM
50Ω
AVEE
V
REF
LPF
BW_SEL
DETECTOR
RSSI/LOS
GENERAL DESCRIPTION
The ADN2892 is a 4.25 Gbps limiting amplifier with integrated
loss of signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for Fibre
Channel (FC) and Gigabit Ethernet (GbE) optoelectronic
conversion applications. The ADN2892 has a differential input
sensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-p
differential input overload voltage. The ADN2892 has current
mode logic (CML) outputs with controlled rise and fall times.
The ADN2892 has a selectable low-pass filter with a −3 dB
cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the
filter can limit the relaxation oscillation of a low cost CD laser
used in a legacy 1 Gbps FC transmitter. The limited BW also
reduces the rms noise and in turn improves the receiver optical
sensitivity for a lower data rate application, such as 1× FC and
GbE.
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch. The ADN2892 is available
in a 3 mm × 3 mm, 16-lead LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SQUELCH
THRADJ
DRVCC DRVEE
50Ω
©2005 Analog Devices, Inc. All rights reserved.
LOS_INV
50Ω
Limiting Amplifier
3.3 V, 4.25 Gbps,
OUTP
OUTN
RSSI_OUT
LOS
V+
10kΩ
ADN2892
ADuC7020
www.analog.com

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ADN2892ACPZ-RL Summary of contents

Page 1

FEATURES Input sensitivity: 3 rise/fall times CML outputs: 750 mV p-p differential Bandwidth selectable for multirate 1×/2×/4× FC modules Optional LOS output inversion Programmable LOS detector: 3 signal strength indicator (RSSI) ...

Page 2

ADN2892 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Limiting Amplifier ..................................................................... 10 Loss-of-Signal (LOS) Detector ...

Page 3

SPECIFICATIONS Test Conditions: VCC = 2 3.6 V, VEE = Table 1. Parameter QUANTIZER DC CHARACTERISTICS Input Voltage Range Input Common Mode Peak-to-Peak Differential Input Range Input Sensitivity Input Offset Voltage Input RMS Noise Input ...

Page 4

ADN2892 Parameter LOGIC INPUTS (SQUELCH, LOS_INV, AND BW_SEL Input High Voltage Input Low Voltage IL Input Current (SQUELCH, LOS_INV) Input Current (BW_SEL) LOGIC OUTPUTS (LOS Output High Voltage Output Low ...

Page 5

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Power Supply Voltage Minimum Voltage (All Inputs and Outputs) Maximum Voltage (All Inputs and Outputs) Storage Temperature Operating Temperature Range Production Soldering Temperature Junction Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges ...

Page 6

ADN2892 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Note that there is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias. Table 4. Pin Function Descriptions Pin No. Mnemonic I/O Type ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS 50ps/DIV Figure 3. Eye of ADN2892 @ 25°C, 4.25 Gbps, and 10 mV Input 50ps/DIV Figure 4. Eye of ADN2892 @ 95°C, 4.25 Gbps, and 10 mV Input 200ps/DIV Figure 5. Eye of ADN2892 at 25°C, 1.063 ...

Page 8

ADN2892 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 1.5 2.0 2.5 3.0 RATE (Gbps) Figure 9. Random Jitter vs. Data Rate 1.0 1.5 2.0 2.5 3.0 RATE ...

Page 9

TEMPERATURE (°C) Figure 15. RSSI Offset—Difference Between Measured RSSI Output and PD_CATHODE (Input) Current of 5 µA 5.0 4.5 4.0 3.5 3.0 2.5 +100 ° ...

Page 10

ADN2892 THEORY OF OPERATION LIMITING AMPLIFIER Input Buffer The ADN2892 limiting amplifier provides differential inputs (PIN/NIN), each with a single-ended, on-chip 50 Ω termination. The amplifier can accept either dc-coupled or ac-coupled signals; however, an ac-coupled signal is recommended. Using ...

Page 11

APPLICATIONS PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used to ensure optimal performance. Output Buffer Power Supply and Ground Planes Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and ground pins that provide current ...

Page 12

ADN2892 PCB Layout Figure 19 shows the recommended PCB layout. The 50 Ω transmission lines are the traces that bring the high frequency input and output signals (PIN, NIN, OUTP, and OUTN) from a terminated source to a terminated load ...

Page 13

... MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADN2892ACPZ-500RL7 1 –40°C to +95°C 1 ADN2892ACPZ-RL7 –40°C to +95°C ADN2892ACPZ-RL 1 –40°C to +95°C EVAL-ADN2892EB Pb-free part. 3.00 0.60 MAX BSC SQ 0.45 2.75 TOP BSC SQ VIEW 0.50 BSC 1 ...

Page 14

ADN2892 NOTES Rev Page ...

Page 15

NOTES Rev Page ADN2892 ...

Page 16

ADN2892 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04986–0–4/05(0) Rev Page ...

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