ADG633YRU Analog Devices Inc, ADG633YRU Datasheet - Page 13

• Manufacturer Part Number: ADG633YRU
• Description: IC,ANALOG SWITCH,TRIPLE,SPDT,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Analog Switchr

Specifications of ADG633YRU

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Function: Switch
• Circuit: 3 x SPDT
• On-state Resistance: 75 Ohm
• Voltage Supply Source: Single, Dual Supply
• Voltage - Supply, Single/dual (±): 2 V ~ 12 V, ±2 V ~ 6 V
• Current - Supply: 0.01µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Multiplexer Configuration: Triple SPDT
• Number Of Inputs: 3
• Number Of Outputs: 6
• Number Of Channels: 3
• Analog Switch On Resistance: 300@3.6VOhm
• Analog Switch Turn On Time: 310ns
• Analog Switch Turn Off Time: 40ns
• Package Type: TSSOP
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 2V
• Single Supply Voltage (typ): 3/5/9V
• Single Supply Voltage (max): 12V
• Dual Supply Voltage (min): ±2V
• Dual Supply Voltage (typ): ±3/±5V
• Dual Supply Voltage (max): ±6V
• Power Dissipation: 0.00001W
• Supply Current: 0.001mA
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Package: 16TSSOP
• Maximum On Resistance: 300@3.6V Ohm
• Maximum Propagation Delay Bus To Bus: 90@±5V|150@5V|300@2.7V ns
• Maximum High Level Output Current: 20 mA
• Maximum Turn-off Time: 40@±5V ns
• Maximum Turn-on Time: 310@3.6V ns
• Switch Architecture: SPDT
• Power Supply Type: Single|Dual
• Lead Free Status / Rohs Status: Not Compliant

LOGIC 1
V
0.1µF
IN
A2
A1
A0
EN
V
V
DD
DD
GND
S
V
50Ω
S
R
D
S
Figure 28. Off Isolation
0.1µF
V
V
V
SS
SS
IN
0.1µF
A2
A1
A0
EN
V
V
ADG633
DD
DD
50Ω
A2
A1
A0
GND
S
EN
OFF ISOLATION = 20 log
ANALYZER
NETWORK
V
ADG633
V
V
S
DD
DD
V
V
SS
GND
SS
S1B
S1A
D1
50Ω
V
V
0.1µF
SS
SS
R
50Ω
D
R
300Ω
ANALYZER
V
NETWORK
L
L
S
50Ω
V
OUT
C
1nF
Figure 26. Enable Delay, t
V
Figure 30. Channel-to-Channel Crosstalk
L
S
V
OUT
V
C
35pF
S
L
V
50Ω
OUT
Figure 27. Charge Injection
V
Rev. A | Page 13 of 16
OUT
0.1µF
SA
DB
A2
A1
A0
ADG633
V
V
LOGIC INPUT
DD
DD
GND
DRIVE (VIN)
V
V
V
SS
SS
CROSSTALK = 20 log
(V
ENABLE
OUTPUT
ON
OUT
3V
0V
0.1µF
EN
DA
IN
V
( EN ), t
)
OUT
3V
0V
0V
OFF
( EN )
0.1µF
A2
A1
A0
EN
V
V
DD
DD
V
V
Q
OUT
50%
GND
S
INJ
S
ANALYZER
NETWORK
R
50Ω
= C
D
INSERTION LOSS = 20 log
V
V
L
0.9V
SS
SS
L
Figure 29. Bandwidth
× ΔV
0.1µF
V
t
ON
OUT
OUT
(EN)
OUT
ΔV
50%
OUT
0.9V
V
OUT
t
V
OFF
OUT
R
50Ω
ANALYZER
OUT
NETWORK
L
WITHOUT SWITCH
(EN)
50Ω
WITH SWITCH
V
OUT
V
S
ADG633