ADF7020-1BCPZ-RL7 Analog Devices Inc, ADF7020-1BCPZ-RL7 Datasheet - Page 20

• Manufacturer Part Number: ADF7020-1BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ-RL7

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020-1
RECEIVER SECTION
RF FRONT END
The ADF7020-1 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power-line-
induced interference problems.
Figure 29 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption for each other in the most
suitable way for their applications. To achieve a high level of
resilience against spurious reception, the LNA features a
differential input. Switch SW2 shorts the LNA input when
transmit mode is selected (R0_DB27 = 0). This feature facili-
tates the design of a combined LNA/PA matching network,
avoiding the need for an external Rx/Tx switch. See the
LNA/PA Matching section for details on the design of the
matching network.
The LNA is followed by a quadrature down conversion mixer,
which converts the RF signal to the IF frequency of 200 kHz. It
is important to consider that the output frequency of the syn-
thesizer must be programmed to a value 200 kHz below the
center frequency of the received channel.
Table 6. LNA/Mixer Modes
Receiver Mode
High Sensitivity Mode (default)
RxMode2
Low Current Mode
Enhanced Linearity Mode
RxMode5
RxMode6
Tx/Rx SELECT
LNA/MIXER ENABLE
[R0_DB27]
LNA CURRENT
[R6_DB(16:17)]
[R9_DB(20:21)]
RFINB
LNA MODE
[R6_DB15]
RFIN
LNA GAIN
[R8_DB6]
Figure 29. ADF7020-1 RF Front End
SW2
LNA
LNA Mode
(R6_DB15)
0
1
1
1
1
0
LNA Gain
Value
R9_DB (21:20)
30
10
3
3
10
30
LO
I (TO FILTER)
Q (TO FILTER)
MIXER LINEARITY
[R6_DB18]
Rev. 0 | Page 20 of 48
Mixer
Linearity
(R6_DB18)
0
0
0
1
1
1
The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA_mode bit, R6_DB15. The mixer is also
configurable between a low current and an enhanced linearity
mode using the mixer_linearity bit, R6_DB18.
Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust control bits
LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as
outlined in Table 6.
The gain of the LNA is configured by the LNA_gain field,
R9_DB (20:21), and can be set by either the user or the
automatic gain control (AGC) logic.
IF Filter Settings/Calibration
Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed
between 100 kHz and 200 kHz by means of Control Bits R1_DB
(22:23); it should be chosen as a compromise between inter-
ference rejection, attenuation of the desired signal, and the AFC
pull-in range.
To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. The IF filter
calibration logic requires that the IF filter divider in
Bits R6_DB (20:28) be set dependent on the crystal frequency.
Once initiated by setting Bit R6_DB19, the calibration is
performed automatically without any user intervention. The
calibration time is 200 μs, during which the ADF7020-1 should
not be accessed. It is important not to initiate the calibration
cycle before the crystal oscillator has fully settled. If the AGC
loop is disabled, the gain of IF filter can be set to three levels
using the filter_gain field, R9_DB (22:23). The filter gain is
adjusted automatically, if the AGC loop is enabled.
Sensitivity
(DR = 9.6 kbps,
f
−112.5
−105.8
−92.2
−102.5
−99
−105
DEV
= 10 kHz)
Rx Current
Consumption
(mA)
20.1
19.0
17.6
17.6
19.0
20.1
Input IP3
(dBm)
−35
−15.9
−3.2
+6.8
−8.25
−28.8