ADF7020-1BCPZ-RL7 Analog Devices Inc, ADF7020-1BCPZ-RL7 Datasheet - Page 35

• Manufacturer Part Number: ADF7020-1BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ-RL7

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

REGISTER 3—RECEIVER CLOCK REGISTER
Notes
1.
2.
3.
4.
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where
Note that this might affect your choice of XTAL, depending on the desired data rate.
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to
40 kHz for ASK:
CDR
BBOS
DEMOD
SEQ
_
_
_
CLK
CLK
CLK
_
CLK
=
=
=
SEQ
CDR
BBOS
=
DEMOD
DEMOD
_
_
CLK
CLK
_
XTAL
SK8
0
0
.
1
1
CLK
XTAL
SEQUENCER CLOCK DIVIDE
_
_
_
DIVIDE
SK7
0
0
.
1
1
_
DIVIDE
XTAL
_
CLK
CLK
DIVIDE
...
...
...
...
...
...
_
DIVIDE
.
.
SK3
0
0
.
1
1
.
SK2
0
1
.
1
1
.
FS8
0
0
.
1
1
SK1
1
0
.
0
1
FS7
0
0
.
1
1
SEQ_CLK_DIVIDE
1
2
.
254
255
...
...
...
...
...
...
Rev. 0 | Page 35 of 48
CDR CLOCK DIVIDE
Figure 46.
FS3
0
0
.
1
1
FS2
0
1
.
1
1
FS1
1
0
.
0
1
CDR_CLK_DIVIDE
1
2
.
254
255
OK2
0
0
1
1
OK1
0
1
0
1
BK2
0
0
1
DEMOD_CLK_DIVIDE
4
1
2
3
BK1
0
1
x
BBOS_CLK_DIVIDE
4
8
16
ADDRESS
BITS
ADF7020-1