ADF4110BRUZ-RL Analog Devices Inc, ADF4110BRUZ-RL Datasheet - Page 3

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ADF4110BRUZ-RL

Manufacturer Part Number
ADF4110BRUZ-RL
Description
SINGLE PLL, 0.55GHz
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of ADF4110BRUZ-RL

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
550MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
550MHz
Number Of Elements
1
Supply Current
5.5mA
Pll Input Freq (min)
5MHz
Pll Input Freq (max)
550MHz
Operating Supply Voltage (typ)
3/5V
Operating Temp Range
-40C to 85C
Package Type
TSSOP
Output Frequency Range
Up to 200MHz
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
Lead Free Status / Rohs Status
Compliant
SPECIFICATIONS
AV
T
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF CHARACTERISTICS (5 V)
REFIN CHARACTERISTICS
PHASE DETECTOR FREQUENCY
CHARGE PUMP
LOGIC INPUTS
LOGIC OUTPUTS
MIN
RF Input Sensitivity
RF Input Frequency
Maximum Allowable Prescaler Output
Frequency
RF Input Sensitivity
RF Input Frequency
Maximum Allowable Prescaler Output
Frequency
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
I
I
Sink and Source Current Matching
I
I
V
V
I
C
V
V
CP
CP
CP
CP
INH
DD
INH
INL
OH
OL
IN
to T
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
Sink/Source
High Value
Low Value
Absolute Accuracy
R
3-State Leakage Current
vs. V
vs. Temperature
, Input Capacitance
/I
, Output Low Voltage
, Input Low Voltage
, Output High Voltage
, Input High Voltage
= DV
SET
INL
, Input Current
Range
MAX
CP
DD
, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
2
2
= 3 V ± 10%, 5 V ± 10%; AV
4
DD
B Version
−15/0
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
−10/0
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
5/104
0.4/AV
3.0/AV
10
±100
55
5
625
2.5
2.7/10
1
2
1.5
2
0.8 × DV
0.2 × DV
±1
10
DV
0.4
≤V
DD
P
– 0.4
≤ 6.0 V; AGND = DGND = CPGND = 0 V; R
DD
DD
DD
DD
B Chips
−15/0
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
−10/0
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
5/104
0.4/AV
3.0/AV
10
±100
55
5
625
2.5
2.7/10
1
2
1.5
2
0.8 × DV
0.2 × DV
±1
10
DV
0.4
DD
Rev. C | Page 3 of 28
– 0.4
DD
DD
1
DD
DD
Unit
dBm min/max
MHz min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
MHz max
dBm min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
MHz max
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V max
ADF4110/ADF4111/ADF4112/ADF4113
Test Conditions/Comments
See Figure 29 for input circuit.
For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
Input level = −10 dBm.
For lower frequencies, ensure SR > 30 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
Input level = −10 dBm.
Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
For lower frequencies, ensure SR > 130 V/µs.
Input level = −5 dBm
For f < 5 MHz, ensure SR > 100 V/µs.
AV
AV
Programmable (see Table 9).
With R
With R
See Table 9.
0.5 V ≤ V
0.5 V ≤ V
V
I
I
OH
OL
CP
DD
DD
= 500 µA.
= 500 µA.
= V
= 3.3 V, biased at AV
= 5 V, biased at AV
SET
SET
P
/2.
SET
CP
CP
= 4.7 kΩ
= 4.7 kΩ
≤ V
≤ V
= 4.7 kΩ; dBm referred to 50 Ω; T
P
P
– 0.5 V.
– 0.5 V.
DD
DD
/2. See Note 3.
/2. See Note 3.
A
=

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