ADF4110BRUZ-RL Analog Devices Inc, ADF4110BRUZ-RL Datasheet - Page 22

• Manufacturer Part Number: ADF4110BRUZ-RL
• Description: SINGLE PLL, 0.55GHz
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4110BRUZ-RL

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 550MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 550MHz
• Number Of Elements: 1
• Supply Current: 5.5mA
• Pll Input Freq (min): 5MHz
• Pll Input Freq (max): 550MHz
• Operating Supply Voltage (typ): 3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: Up to 200MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / Rohs Status: Compliant

ADF4110/ADF4111/ADF4112/ADF4113
APPLICATIONS
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used
with a VCO to produce the LO for a GSM base station
transmitter.
The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical GSM system
would have a 13 MHz TCXO driving the reference input with-
out any 50 Ω termination. In order to have channel spacing of
200 kHz (GSM standard), the reference input must be divided
by 65, using the on-chip reference divider of the ADF4111/
ADF4112/ADF4113.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter
component values, a number of items need to be considered. In
this example, the loop filter was designed so that the overall
phase margin for the system would be 45 degrees. Other PLL
system specifications are
K
K
Loop Bandwidth = 20 kHz
F
N = 4500
Extra Reference Spur Attenuation = 10 dB
REF
D
V
= 12 MHz/V
= 5 mA
= 200 kHz
FREF
IN
1000pF
51Ω
1
4.7kΩ
1000pF
1
8
CE
CLK
DATA
LE
AV
REF
3
R
V
7
DD
DD
SET
ADF4111
ADF4112
ADF4113
IN
4
DV
MUXOUT
15
DD
9
Figure 33. Local Oscillator for GSM Base Station
RF
RF
IN
IN
CP
V
V
16
A
B
P
P
14
2
6
5
IN
100pF
100pF
Rev. C | Page 22 of 28
1nF
LOCK
DETECT
1
2
DECOUPLING CAPACITORS ON AV
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω.
OPTIONAL MATCHING RESISTOR DEPENDING ON RF
51Ω
5.6kΩ
8.2nF
3.3kΩ
2
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 33.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF out-
put terminal. A T-circuit configuration provides 50 Ω matching
between the VCO output, the RF output, and the RF
of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 33, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
620pF
C
V
VCO190-902T
CC
B
DD
, DV
DD
, AND V
P
100pF
P
OF THE ADF411x
OUT
FREQUENCY.
100pF
18Ω
18Ω
18Ω
RF
OUT
IN
terminal