AD9861BCP-50 Analog Devices Inc, AD9861BCP-50 Datasheet - Page 41

• Manufacturer Part Number: AD9861BCP-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9861BCP-50

• Rohs Status: RoHS non-compliant
• Rf Type: WLL, WLAN
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Bit
Register 23: AuxADC
Registers 24, 25, 26: AuxDAC
Register 28: AuxDAC
Register 29: AuxDAC
Bits 1,0: AuxADC Clock Div
AuxDAC A, B, and C Output
Control Word
Bit 7: Slave Enable
Bits 2/1/0: Update C, B, and A
Bits 7/6/5: AuxDAC C/B/A Sync
TxPwrDwn
Bits 2/1/0: Power Up C, B, and A
Description
The AuxADCs clock can be based on either the clock driving the Rx ADC, or it can be driven from
the SPI_CLK. The conversion rate of the AuxADCs should be less than 40 MHz. In order to facilitate a
slower speed clock for the AuxADC, these bits are used to divide down the Rx ADC clock prior to
driving the AuxADC. The following options are programmable through this register:
Three 8-bit, straight binary words are used to control the output of three on-chip AuxDACs. The
AuxDAC output changes take effect immediately after any of the serial writes are completed. The
DAC output control words have default values of 0. The smaller programmed output controlled
words correspond to lower DAC output levels.
A low setting (default) updates the AuxDACs after the respective register is written to. To
synchronize the AuxDAC outputs to each other, a slave mode can be enabled by setting this bit
high and then setting the appropriate update registers high.
Setting a high bit to any of these bits initiates an update of the respective AuxDAC, A, B or C, when
slave mode is enabled using the slave enable register. The register bit is a one-shot and always
reads back a low. Be sure to keep the slave enable bit high when using the AuxDAC synchronization
option.
Setting any of these bits high synchronizes AuxDAC updates only when the TxPwrDwn rising edge
occurs. This syncronizes the AuxDAC update to the Tx path power-up.
Setting any of these bits high powers up the appropriate AuxDAC. By default, these bits are low and
the AuxDACs are disabled.
MSB, LSB
00
01
10
11
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AuxADC Sampling Rate
Rx ADC Clock/4
Rx ADC Clock/2
Rx ADC Clock
SPI_CLK drives AuxADC
AD9861