AD9854/PCBZ Analog Devices Inc, AD9854/PCBZ Datasheet - Page 43

• Manufacturer Part Number: AD9854/PCBZ
• Description: 300 MHZ QUADRATURE DDS SYN. Eval Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9854/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9854
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

attached to each header to allow the DAC signals to be routed
to the filters. If the user wishes to test the filters, the shorting
jumpers at W7 and W10 should be removed and 50 Ω test
signals should be applied at the J4 and J5 inputs to the 50 Ω
elliptic filters. Users should refer to the schematic provided and to
the following sections to properly position the remaining
shorting jumpers.
Observing the Unfiltered IOUT1 and the Unfiltered
IOUT2 DAC Signals
The unfiltered DAC outputs can be observed at J5 (the I, or
cosine DAC, signal) and J4 (the Q, or control DAC, signal). Use
the following procedure to route the two 50 Ω terminated
analog DAC outputs to the SMB connectors and to disconnect
any other circuitry:
1.
2.
3.
4.
The raw DAC outputs may appear as a series of quantized
(stepped) output levels that may not resemble a sine wave until
they are filtered. The default 10 mA output current develops a
0.5 V p-p signal across the on-board 50 Ω termination. If the
observation equipment offers 50 Ω inputs, the DAC develops
only 0.25 V p-p due to the double termination.
If using the AD9852 evaluation board, the user can control
IOUT2 (the control DAC output) by using the serial or parallel
ports. The 12-bit, twos complement value(s) is/are written to
the control DAC register that sets the IOUT2 output to a static
dc level. Allowable hexadecimal values are 7FF (maximum) to
800 (minimum), with all 0s being midscale. Rapidly changing
the contents of the control DAC register (up to 100 MSPS)
allows IOUT2 to assume any waveform that can be
programmed.
Observing the Filtered IOUT1 and the Filtered IOUT2
The filtered I (cosine DAC) and Q (control DAC) outputs can
be observed at J6 (for the I signal) and J7 (for the Q signal). Use
the following procedure to route the 50 Ω (input and output Z)
low-pass filters into the pathways of the I and Q signals to
remove images, aliased harmonics, and other spurious signals
that are greater than approximately 120 MHz:
1.
2.
3.
4.
5.
Install shorting jumpers at W7 and W10.
Remove the shorting jumper at W16.
Remove the shorting jumper from the 3-pin W1 header.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the 3-pin W4 header.
Install shorting jumpers at W7 and W10.
Install a shorting jumper at W16.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)
of the 3-pin W1 header.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)
of the 3-pin W4 header.
Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)
of the 3-pin W2 and W8 headers.
Rev. E | Page 43 of 52
The resulting I and Q signals appear as nearly pure sine waves
and 90° out of phase with each other. These filters are designed
with the assumption that the system clock speed is at or near its
maximum speed (300 MHz). If the system clock speed is much
less than 300 MHz, for example 200 MHz, it is possible, or
inevitable, that unwanted DAC products other than the
fundamental signal will be passed by the low-pass filters.
If the AD9852 evaluation board is used, any reference to the Q
signal should be interpreted as meaning the control DAC.
Observing the Filtered IOUT1 and the Filtered IOUT1
The filtered I DAC outputs can be observed at J6 (the true signal)
and J7 (the complementary signal). Use the following procedure to
route the 120 MHz low-pass filters in the true and complementary
output paths of the I DAC to remove images, aliased harmonics,
and other spurious signals that are greater than approximately
120 MHz:
1.
2.
3.
4.
5.
The resulting signals appear as nearly pure sine waves and 180°
out of phase with each other. If the system clock speed is much
less than 300 MHz, for example 200 MHz, it is possible, or
inevitable, that unwanted DAC products other than the
fundamental signal will be passed by the low-pass filters.
Connecting the High Speed Comparator
To connect the high speed comparator to the DAC output
signals use either the quadrature filtered output configuration
(for AD9854 only) or the complementary filtered output
configuration outlined in the previous section (for both the
AD9854 and the AD9852). Follow Step 1 through Step 4 in
either the Observing the Filtered IOUT1 and the Filtered
IOUT2 section or the Observing the Filtered IOUT1 and the
Filtered IOUT1 section. Then install a shorting jumper on Pin 1
and Pin 2 (top two pins) of the 3-pin W2 and W8 headers. This
reroutes the filtered signals away from the output connectors
(J6 and J7) and to the 100 Ω configured comparator inputs.
This sets up the comparator for differential input without
affecting the comparator output duty cycle, which should be
approximately 50% in this configuration.
The user can change the value of R
to 1.95 kΩ to receive more robust signals at the comparator
inputs. This decreases jitter and extends the operating range of
the comparator. To implement this change install a shorting
jumper at W6, which provides a second 3.9 kΩ chip resistor
(R20) in parallel with that provided by R2. This boosts the DAC
Install shorting jumpers at W7 and W10.
Install a shorting jumper at W16.
Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W1 header.
Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W4 header.
Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)
of the 3-pin W2 and W8 headers.
SET
Resistor R2 from 3.9 kΩ
AD9854