AD9854/PCBZ Analog Devices Inc, AD9854/PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9854/PCBZ
• Description: 300 MHZ QUADRATURE DDS SYN. Eval Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9854/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9854
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8. Register Layout
Parallel
Address
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
1
The shaded sections comprise the control register.
Serial
Address
(Hex)
0
1
2
3
4
5
6
7
8
9
A
B
Bit 7
Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care)
Phase Adjust Register 1 <7:0>
Phase Adjust Register 2 <13:8> (Bits 15, 14, don’t care)
Phase Adjust Register 2 <7:0>
Frequency Tuning Word 1 <47:40>
Frequency Tuning Word 1 <39:32>
Frequency Tuning Word 1 <31:24>
Frequency Tuning Word 1 <23:16>
Frequency Tuning Word 1 <15:8>
Frequency Tuning Word 1 <7:0>
Frequency Tuning Word 2 <47:40>
Frequency Tuning Word 2 <39:32>
Frequency Tuning Word 2 <31:24>
Frequency Tuning Word 2 <23:16>
Frequency Tuning Word 2 <15:8>
Frequency Tuning Word 2 <7:0>
Delta frequency word <47:40>
Delta frequency word <39:32>
Delta frequency word <31:24>
Delta frequency word <23:16>
Delta frequency word <15:8>
Delta frequency word <7:0>
Update clock <31:24>
Update clock <23:16>
Update clock <15:8>
Update clock <7:0>
Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)
Ramp rate clock <15:8>
Ramp rate clock <7:0>
Don’t
care
CR [31]
Don’t
care
CLR
ACC 1
Don’t
care
Output shaped keying I multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
Output shaped keying I multiplier <7:0>
Output shaped keying Q multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
Output shaped keying Q multiplier <7:0>
Output shaped keying ramp rate <7:0>
QDAC <11:8> (Bits 15, 14, 13, 12 don’t care)
QDAC <7:0> (data is required to be in twos complement format)
1
Bit 6
Don’t
care
PLL
range
CLR
ACC 2
Bypass
inv sinc
Bit 5
Don’t
care
Bypass
PLL
Triangle
OSK EN
Bit 4
Comp
PD
Ref
Mult 4
SRC
QDAC
OSK
INT
AD9854 Register Layout
Rev. E | Page 33 of 52
Bit 3
Reserved,
always low
Ref Mult 3
Mode 2
Don’t care
Bit 2
Phase 1
Phase 2
Freq 1
QDAC PD
Ref Mult 2
Mode 1
Don’t care
Bit 1
DAC PD
Ref
Mult 1
Mode 0
LSB first
Bit 0
DIG PD
Ref Mult 0
Internal/external
update clock
SDO active CR [0]
Default
Value
(Hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
40
00
00
00
10
64
01
20
00
00
00
00
80
00
AD9854