AD9776ABSVZRL Analog Devices Inc, AD9776ABSVZRL Datasheet - Page 2

• Manufacturer Part Number: AD9776ABSVZRL
• Description: IC,D/A CONVERTER,DUAL,12-BIT,CMOS,TQFP,100PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9776ABSVZRL

• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9776A-EBZ - BOARD EVALUATION AD9776A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Serial Peripheral Interface ............................................................. 24
SPI Register Map ............................................................................. 26
Interpolation Filter Architecture .................................................. 31
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Added Note 2 .................................................................................... 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Thermal Resistance Section ........................................ 7
Inserted Table 6 ................................................................................. 8
Changes to Pin 39 Description, Table 7 ......................................... 9
Changes to Pin 39 Description, Table 8 ....................................... 10
Changes to Pin 39 Description, Table 9 ....................................... 12
Changes to Theory of Operation Section .................................... 23
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Digital Input Data Timing Specifications ................................. 6
AC Specifications .......................................................................... 6
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Differences Between AD9776/AD9778/ AD9779 and
AD9776A/AD9778A/AD9779A............................................... 23
General Operation of the Serial Interface ............................... 24
Instruction Byte .......................................................................... 24
Serial Interface Port Pin Descriptions ..................................... 25
MSB/LSB Transfers..................................................................... 25
Interpolation Filter Bandwidth Limits .................................... 35
Rev. A | Page 2 of 60
Sourcing the DAC Sample Clock ................................................. 36
Full-Scale Current Generation ..................................................... 39
Transmit Path Gain and Offset Correction................................. 40
Input Data Ports ............................................................................. 42
Device Synchronization ................................................................. 45
Power Dissipation ........................................................................... 47
Evaluation Board Operation ......................................................... 49
Outline Dimensions ....................................................................... 60
Changes to Table 10 ....................................................................... 23
Changes to Table 13 ....................................................................... 26
Changes to Table 14 ....................................................................... 27
Changes to Interpolation Filter Architecture Section ............... 33
Replaced Sourcing the DAC Sample Clock Section .................. 36
Replaced Transmit Path Gain and Offset Correction Section . 40
Replaced Input Data Ports Section .............................................. 42
Replaced Device Synchronization Section .................................. 45
Deleted Figure 112 to Figure 117 ................................................. 58
8/07—Revision 0: Initial Version
Direct Clocking .......................................................................... 36
Clock Multiplication .................................................................. 36
Driving the REFCLK Input ....................................................... 38
Internal Reference ...................................................................... 39
I/Q Channel Gain Matching ..................................................... 40
Auxiliary DAC Operation ......................................................... 40
LO Feedthrough Compensation .............................................. 41
Results of Gain and Offset Correction .................................... 41
Single Port Mode ........................................................................ 42
Dual Port Mode .......................................................................... 42
Input Data Referenced to DATACLK ...................................... 42
Input Data Referenced to REFCLK ......................................... 43
Optimizing the Data Input Timing .......................................... 44
Synchronization Logic Overview ............................................. 45
Synchronizing Devices to a System Clock .............................. 46
Interrupt Request Operation .................................................... 46
Power-Down and Sleep Modes................................................. 48
Using the ADL5372 Quadrature Modulator .......................... 51
Evaluation Board Schematics ................................................... 52
Ordering Guide .......................................................................... 60