AD9752AR Analog Devices Inc, AD9752AR Datasheet
AD9752AR
Specifications of AD9752AR
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AD9752AR Summary of contents
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FEATURES High Performance Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 79 dBc Differential Current Outputs Power ...
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AD9752–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + MIN MAX Differential Nonlinearity (DNL + MIN MAX ANALOG ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to ...
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... LPW 0.1% Figure 1. Timing Diagram Max Units Model +6.5 V AD9752AR +6.5 V AD9752ARU – +85 C 28-Lead TSSOP +0.3 V AD9752-EB +6.5 V DVDD + 0 Small Outline IC Thin Shrink Small Outline Package. DVDD + 0.3 V THERMAL CHARACTERISTICS AVDD + 0.3 V Thermal Resistance AVDD + 0.3 V 28-Lead 300 Mil SOIC AVDD + 0 ...
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Pin No. Name Description 1 DB11 Most Significant Data Bit (MSB). 2–11 DB10–DB1 Data Bits 1–10. 12 DB0 Least Significant Data Bit (LSB). 13, 14, 19 Internal Connection. 15 SLEEP Power-Down Control Input. Active High. Contains active ...
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AD9752 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. ...
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Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = + mA, 50 OUTFS 90 50MSPS 25MSPS 80 70 125MSPS 65MSPS 100 f – MHz OUT ...
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AD9752 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 0 1000 2000 3000 4000 CODE Figure 12. Typical INL 125MSPS CLK – 13.5MHz OUT1 – 14.5MHz OUT2 A = ...
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V REFIO I REF 0 SET 2k +5V CLOCK CLOCK FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9752. The AD9752 consists of a large PMOS current source array that is capable of providing up ...
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AD9752 REFERENCE OPERATION The AD9752 contains an internal 1.20 V bandgap reference that can easily be disabled and overridden by an external refer- ence. REFIO serves as either an input or output depending on whether the internal or an external ...
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The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and I varied by an external voltage applied fier. An example of this method is shown ...
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AD9752 In summary, the AD9752 achieves the optimum distortion and noise performance under the following conditions: (1) Differential Operation. (2) Positive voltage swing at IOUTA and IOUTB limited to +0.5 V. (3) I set to 20 mA. OUTFS (4) Analog ...
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SLEEP MODE OPERATION The AD9752 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2 5.5 V and temperature range. This ...
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AD9752 MINI-CIRCUITS T1-1T IOUTA AD9752 IOUTB OPTIONAL R Figure 28. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA ...
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C OPT R FB 200 I = 10mA AD9752 OUTFS IOUTA U1 IOUTB 200 Figure 32. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating ...
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AD9752 maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. ...
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AD9752 DSP CARRIER OR FREQUENCY ASIC 12 AD9752 NYQUIST FILTERS Figure 36. Typical Analog QAM Architecture In this implementation much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit ...
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AD9752 DVDD REFLO REFIO AD9752 (“I DAC”) U1 FSADJ DAC R SET1 2k LATCHES I DATA INPUT CLK AVDD REFLO LATCHES Q DATA U2 INPUT DAC AD9752 (“Q DAC”) REFIO FSADJ R SET2 1.9k 0 CAL 220 ACOM ...
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REV. 0 Figure 41. Evaluation Board Schematic –19– AD9752 ...
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AD9752 Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) –20– REV. 0 ...
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REV. 0 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –21– AD9752 ...
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AD9752 Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom –22– REV. 0 ...
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SEATING PLANE REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 ...